Freescale Semiconductor MPC8260 - Manual (Page 43)

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor xli
Contents
Paragraph
Number
Title
Page
Number
35.15 Handling Collisions ..................................................................................................... 35-17
35.16 Internal and External Loopback................................................................................... 35-17
35.17 Ethernet Error-Handling Procedure ............................................................................. 35-17
35.18 Fast Ethernet Registers ................................................................................................ 35-18
35.18.1 FCC Ethernet Mode Register (FPSMR) .................................................................. 35-18
35.18.2 Ethernet Event Register (FCCE)/Mask Register (FCCM) ...................................... 35-20
35.19 Ethernet RxBDs ........................................................................................................... 35-22
35.20 Ethernet TxBDs ........................................................................................................... 35-25
Chapter 36
FCC HDLC Controller
36.1 Key Features .................................................................................................................. 36-1
36.2 HDLC Channel Frame Transmission Processing .......................................................... 36-2
36.3 HDLC Channel Frame Reception Processing ............................................................... 36-3
36.4 HDLC Parameter RAM ................................................................................................. 36-3
36.5 Programming Model ...................................................................................................... 36-5
36.5.1 HDLC Command Set................................................................................................. 36-5
36.5.2 HDLC Error Handling ............................................................................................... 36-6
36.6 HDLC Mode Register (FPSMR) ................................................................................... 36-7
36.7 HDLC Receive Buffer Descriptor (RxBD).................................................................... 36-9
36.8 HDLC Transmit Buffer Descriptor (TxBD) ................................................................ 36-12
36.9 HDLC Event Register (FCCE)/Mask Register (FCCM) ............................................. 36-14
36.10 FCC Status Register (FCCS) ....................................................................................... 36-16
Chapter 37
FCC Transparent Controller
37.1 Features .......................................................................................................................... 37-1
37.2 Transparent Channel Operation ..................................................................................... 37-2
37.3 Achieving Synchronization in Transparent Mode ......................................................... 37-2
37.3.1 In-Line Synchronization Pattern................................................................................ 37-2
37.3.2 External Synchronization Signals .............................................................................. 37-3
37.3.3 Transparent Synchronization Example ...................................................................... 37-3
Chapter 38
Serial Peripheral Interface (SPI)
38.1 Features .......................................................................................................................... 38-1
38.2 SPI Clocking and Signal Functions ............................................................................... 38-2
38.3 Configuring the SPI Controller...................................................................................... 38-3