Freescale Semiconductor MPC8260 - Manual (Page 955)

ATM Controller and AAL0, AAL1, and AAL5
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 30-35
30.9.3 Timing Issues
Use of the TDM interface assumes that all communicating entities are synchronized (that is, that they are
using a synchronized serial clock). If the TDM interfaces are not synchronized, a slip can occur in the
reassembly buffer. If a buffer-not-ready event occurs at the MCC transmitter, the user must restart the
MCC transmit channel. If a buffer-not-ready event occurs at the ATM transmitter, the user must restart the
ATM transmit channel.
30.9.4 Clock Synchronization (SRTS and Adaptive FIFOs)
Clock synchronization methods, such as using a time stamp (SRTS) or adaptive FIFOs, prevent buffer
slipping during reassembly. The SRTS method may be implemented using external logic. The
PowerQUICC II can read the SRTS from external logic and insert it into AAL1 CES cells, and can track
the SRTS from AAL1 CES cells and deliver it to external logic. See
Section 30.15, “SRTS Generation and
Clock Recovery Using External Logic.”
Alternatively, an adaptive FIFOs method can be implemented using the core to maintain the bridging
buffer at a mid-level point. The difference between the MCC and ATM data pointers is a measure of buffer
synchronization. The core calculates the difference between pointers at regular intervals and adapts the
TDM clock accordingly to hold the difference constant.
30.9.5 Mapping TDM Time Slots to VCs
Using the MCC and the SI, any TDM time-slot combination can be routed to a specific data buffer. (See
Chapter 28, “Multi-Channel Controllers (MCCs),” and Chapter 15, “Serial Interface with Time-Slot
Assigner.” ) The same data buffers should be used by the ATM controller to route receive and transmit data.
For information about ATM buffers see Section 30.10.5, “ATM Controller Buffer Descriptors (BDs).”
30.9.6 CAS Support
For applications requiring channel-associated signaling (CAS), circuit emulation with CAS requires
additional core processing. External framers perform the CAS manipulation through a serial or parallel
interface.
When the MCC receives a multi-frame block, it generates an interrupt to the core. The core reads the CAS
block from the external framer and places it at the end of the ATM data buffer after the structured
multi-frame block. The core then passes the buffer pointer to the ATM controller, and the controller packs
the data and CAS block into AAL1 CES cells. All AAL1 CES functions, such as generating PDU-headers
and structured pointers, operate normally.
When the ATM controller receives a multi-frame block, it generates an interrupt to the core. The core reads
the CAS block from the data buffer and writes it to the external framer. The core then moves the buffer
pointer to the MCC. The buffer’s data length should not include the CAS octets.
To optimize the process, the framer may interrupt the core only when the CAS information changes. (CAS
information changes slowly.) The core can keep the CAS block in memory and connect to the framer only
when the CAS changes. The core can use regular read and write cycles when connecting to the framer
through a parallel interface.