Freescale Semiconductor MPC8260 - Manual (Page 747)

SCC HDLC Mode
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 22-19
While in the active condition (ready to transmit), the HDLC bus controller monitors the bus using CTS. It
counts the one bits on CTS. When eight consecutive ones are counted, the HDLC bus controller starts
transmitting on the line; if a zero is detected, the internal counter is cleared. During transmission, data is
continuously compared with the external bus using CTS. CTS is sampled halfway through the bit time
using the rising edge of the Tx clock. If the transmitted bit matches the received CTS bus sample,
transmission continues. However, if the received CTS sample is 0 and the transmitted bit is 1, transmission
stops after that bit and waits for an idle line before attempting retransmission. Since the HDLC bus uses a
wired-OR scheme, a transmitted zero has priority over a transmitted 1.
Figure 22-12 shows how CTS is
used to detect collisions.
Figure 22-12. Detecting an HDLC Bus Collision
If both the destination address and source address are included in the HDLC frame, then a predefined
priority of stations results; if two stations begin to transmit simultaneously, they necessarily detect a
collision no later than the end of the source address.
The HDLC bus priority mechanism ensures that stations share the bus equally. To minimize idle time
between messages, a station normally waits for eight one bits on the line before attempting transmission.
After successfully sending a frame, a station waits for 10 rather than eight consecutive one bits before
attempting another transmission. This mechanism ensures that another station waiting to transmit acquires
the bus before a station can transmit twice. When a low priority station detects 10 consecutive ones, it tries
to transmit; if it fails, it reinstates the high priority of waiting for only eight ones.
22.15.3 Increasing Performance
Because it uses a wired-OR configuration, HDLC bus performance is limited by the rise time of the one
bit. To increase performance, give the one bit more rise time by using a clock that is low longer than it is
high, as shown in
Figure 22-13 .
TCLK
CTS
(Input)
TXD
(Output)
CTS sampled at halfway point.
Collision detected when
TXD=1, but CTS=0.