Freescale Semiconductor MPC8260 - Manual (Page 139)

G2 Core
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 2-21
2.5 Exception Model
This section describes the PowerPC exception model and implementation-specific details of the
PowerQUICC II core.
2.5.1 PowerPC Exception Model
The PowerPC exception mechanism allows the processor to change to supervisor state as a result of
external signals, errors, or unusual conditions arising in the execution of instructions. When exceptions
occur, information about the state of the processor is saved to certain registers and the processor begins
execution at an address (exception vector) predetermined for each exception. Processing of exceptions
occurs in supervisor mode.
Although multiple exception conditions can map to a single exception vector, a more specific condition
may be determined by examining a register associated with the exception—for example, the DSISR
identifies instructions that cause a DSI exception. Additionally, some exception conditions can be
explicitly enabled or disabled by software.
The PowerPC architecture requires that exceptions be handled in program order; therefore, although a
particular implementation may recognize exception conditions out of order, exceptions are taken in strict
order. When an instruction-caused exception is recognized, any unexecuted instructions that appear earlier
in the instruction stream, including any that have not yet entered the execute stage, are required to complete
before the exception is taken. Any exceptions caused by those instructions are handled first. Likewise,
exceptions that are asynchronous and precise are recognized when they occur, but are not handled until the
instruction currently in the completion stage successfully completes execution or generates an exception,
and the completed store queue is emptied.
Unless a catastrophic condition causes a system reset or machine check exception, only one exception is
handled at a time. If, for example, a single instruction encounters multiple exception conditions, those
conditions are handled sequentially. After the exception handler handles an exception, the instruction
execution continues until the next exception condition is encountered. However, in many cases there is no
attempt to re-execute the instruction. This method of recognizing and handling exception conditions
sequentially guarantees that exceptions are recoverable.
Exception handlers should save the information stored in SRR0 and SRR1 early to prevent the program
state from being lost due to a system reset or machine check exception or to an instruction-caused
exception in the exception handler. SRR0 and SRR1 should also be saved before enabling external
interrupts.
The PowerPC architecture supports four types of exceptions:
• Synchronous, precise—These are caused by instructions. All instruction-caused exceptions are
handled precisely; that is, the machine state at the time the exception occurs is known and can be
completely restored. This means that (excluding the trap and system call exceptions) the address
of the faulting instruction is provided to the exception handler and that neither the faulting
instruction nor subsequent instructions in the code stream will complete execution before the
exception is taken. Once the exception is processed, execution resumes at the address of the
faulting instruction (or at an alternate address provided by the exception handler). When an