Freescale Semiconductor MPC8260 - Manual (Page 1089)

ATM AAL2
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 32-27
32.4.4.2 CID Mapping Tables and RxQDs
Each PHY | VP | VC | CID combination is assigned an RxQD using a CID mapping table. To multiplex
several receive CIDs into a single common queue, map each multiplexed PHY | VP | VC | CID
combination to one RxQD.
The ATM channel’s RCT contains the base address of the associated CID mapping table. This base address
is external (32 bits) when RCT[MAP]=1; otherwise, the table resides in the dual-port RAM and the base
address is two bytes. The CID of the received packet is used as an index into the mapping table. The
mapping table entries are 2-byte RxQD offsets. If the CID mapping table is external, it must be on the same
bus as the BDs and interrupt queues as specified by RCT[BIB].
There are two RxQDs—one for internal RxQDs and one for external RxQDs. Offsets between 0–511
belong to the 2048-byte internal RxQD table. It is recommended to have as many RxQDs as possible in
the internal table. Note that the first 32 bytes of the internal RxQD table are reserved for internal use; that
is, RxQD offsets between 0–7 are reserved. The address of an internal RxQD is RxQD_Base_Int +
4*RxQD_Offset.
Offsets between 512–65535 belong to the external RxQD table. The address of an external RxQD is
RxQD_Base_Ext + 4*RxQD_Offset. The external RxQD table must be on the same bus as the BDs and
interrupt queues as specified by RCT[BIB].
Because the three kinds of RxQDs are each a different size (for example, an SSSAR RxQD is 32 bytes and
a CPS switch RxQD is only 4 bytes), some of the offset numbers are left unused.
32.4.4.3 CPS Rx Queue Descriptors
Each CPS RxQD, as shown in Figure 32-16 , points to an CPS RxBD table.
Table 32-7 describes the CPS RxQD fields.
0 11 12 13 14 15
Offset + 0x00 — RBM — SubType
Offset + 0x02 RxBD Table Offset
Offset + 0x04 RxBD Table Base
Offset + 0x06
Figure 32-16. CPS Rx Queue Descriptor