Table 40-1. podrx field descriptions, 2 port data registers (pdata-pdatd), Port data registers (pdata–pdatd) -2 – Freescale Semiconductor MPC8260 User Manual
Page 1280: Port open-drain registers (podra–podrd) -2, Podrx field descriptions -2, 2 port data registers (pdata–pdatd), Table 40-1 describes podr fields
Parallel I/O Ports
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
40-2
Freescale Semiconductor
describes PODR fields.
40.2.2
Port Data Registers (PDATA–PDATD)
A read of a port data register (PDATx), shown in
, returns the data at the pin, independent of
whether the pin is defined as an input or output. This allows detection of output conflicts at the pin by
comparing the written data with the data on the pin.
A write to the PDATx is latched and if the equivalent PDIR bit is configured as an output, the value latched
for that bit is driven onto its respective pin. PDATx can be read or written at any time and is not initialized.
If a port pin is selected as a general-purpose I/O pin, it can be accessed through the port data register
(PDATx). Data written to the PDATx is stored in an output latch. If a port pin is configured as an output,
the output latch data is gated onto the port pin. In this case, when PDATx is read, the port pin itself is read.
If a port pin is configured as an input, data written to PDATx is still stored in the output latch, but is
prevented from reaching the port pin. In this case, when PDATx is read, the state of the port pin is read.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Field OD0
1
OD1
1
OD2
1
OD3
1
OD4
OD5
OD6
OD7
OD8
OD9 OD10 OD11 OD12 OD13 OD14 OD15
Reset
0000_0000_0000_0000
R/W
R/W
Addr
0x0x10D0C (PODRA), 0x0x10D2C (PODRB), 0x0x10D4C (PODRC), 0x0x10D6C (PODRD)
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Field OD16 OD17 OD18 OD19 OD20 OD21 OD22 OD23 OD24 OD25 OD26 OD27 OD28 OD29 OD30 OD31
Reset
0000_0000_0000_0000
R/W
R/W
Addr
0x10D0E (PODRA), 0x10D2E (PODRB), 0x10D4E (PODRC), 0x10D6E (PODRD)
1
These bits are valid for PODRA and PODRC only
Figure 40-1. Port Open-Drain Registers (PODRA–PODRD)
Table 40-1. PODR
x Field Descriptions
Bits
Name
Description
0–31
OD
x
Open-drain configuration. Determines whether the corresponding pin is actively driven as an output
or is an open-drain driver. Note that bits OD0–OD3 are valid for PODRA and PODRC only.
0 The I/O pin is actively driven as an output.
1 The I/O pin is an open-drain driver. As an output, the pin is driven active-low, otherwise it is
three-stated.