Freescale Semiconductor MPC8260 - Manual (Page 331)

PCI Bridge
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 9-25
are routed to the PCI bus with address translation disabled. The reset configuration for inbound
transactions are that all inbound requests from the PCI bus are disabled.
9.10.2.1 PCI Inbound Translation
For inbound transactions (transactions generated by an external master on the PCI bus where the PCI
bridge responds as a slave device), the PCI bridge only responds to PCI addresses within the windows
mapped by the PCI inbound base address registers (PIBARs). If there is an address hit in one of the
PIBARs, the PCI address is translated from PCI space to local memory space through the associated PCI
inbound translation address registers (PITARs). This allows an external master to access local memory on
the 60x’s bus. Each PIBAR register is associated with a PITAR and PICMR (PCI inbound comparison
mask register) which are located in the PCI bridge’s PCI internal register space.
Figure 9-15 shows an
example translation window for inbound memory accesses.
Figure 9-15. Inbound PCI Memory Address Translation
There are two sets of inbound translation registers, allowing two simultaneous translation windows.
Software can move the translation base addresses during run-time to access different portions of local
memory, but be sure that the PCI inbound translation windows do not overlap.
The reset configuration for the windows is disabled; that is, after reset, the PCI bridge does not
acknowledge externally mastered transactions on the PCI bus by asserting DEVSEL until the inbound
translation windows are enabled. The inbound translation is performed in the PCI interface.
60x bus view PCI memory view
0 0
4G 4G
Peripheral memory
window
Local memory
PCI memory
System memory
Local peripheral
memory
PCI memory
Inbound address
translation
PCI inbound
translation
address
PCI inbound
window size
PCI inbound
base
address
PCI inbound
window size