Freescale Semiconductor MPC8260 - Manual (Page 742)

SCC HDLC Mode
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
22-14 Freescale Semiconductor
22.12 SCC HDLC Status Register (SCCS)
The SCC status register (SCCS), shown in Figure 22-9 , permits monitoring of real-time status conditions
on RXD. The real-time status of CTS and CD are part of the port C parallel I/O.
Table 22-10 describes HDLC SCCS fields.
22.13 SCC HDLC Programming Examples
The following sections show examples for programming SCCs in HDLC mode. The first example uses an
external clock. The second example implements Manchester encoding.
22.14 SCC HDLC Programming Example #1
The following initialization sequence is for an SCC HDLC channel with an external clock. SCC2 is used
with RTS2, CTS2, and CD2 active; CLK3 is used for both the HDLC receiver and transmitter.
1. Configure port D pins to enable TXD2 and RXD2. Set PPARD[27,28] and PDIRD[27] and clear
PDIRD[28] and PSORD[27,28].
2. Configure ports C and D pins to enable RTS2, CTS2 and CD2. Set PPARD[26], PPARC[12,13]
and PDIRD[26] and clear PDIRC[12,13], PSORC[12,13] and PSORD[26].
0 4 5 6 7
Field — FG CS ID
Reset 0000_0000
R/W R
Addr 0x0x11A17 (SCCS1); 0x0x11A37 (SCCS2); 0x0x11A57 (SCCS3); 0x0x11A77 (SCCS4)
Figure 22-9. CC HDLC Status Register (SCCS)
Table 22-10. HDLC SCCS Field Descriptions
Bits Name Description
0–4 — Reserved, should be cleared.
5 FG Flags. The line is checked after the data has been decoded by the DPLL.
0 HDLC flags are not being received. The most recently received 8 bits are examined every bit time
to see if a flag is present.
1 HDLC flags are being received. FG is set as soon as an HDLC flag (0x7E) is received on the line.
Once it is set, it remains set at least 8 bit times and the next eight received bits are examined. If
another flag occurs, FG stays set for at least another eight bits. If not, it is cleared and the search
begins again.
6 CS Carrier sense (DPLL). Shows the real-time carrier sense of the line as determined by the DPLL.
0 The DPLL does not sense a carrier.
1 The DPLL senses a carrier.
7 ID Idle status.
0 The line is busy.
1 Set when RXD is a logic 1 (idle) for 15 or more consecutive bit times. It is cleared after a single
logic 0 is received.