6 powerquicc ii configurations, 1 pin configurations, 2 serial performance – Freescale Semiconductor MPC8260 User Manual

Page 107: Table 1-2. serial performance, Powerquicc ii configurations -13, Pin configurations -13, Serial performance -13

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Overview

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2

Freescale Semiconductor

1-13

1.6

PowerQUICC II Configurations

The PowerQUICC II offers flexibility in configuring the device for specific applications. The functions
mentioned in the above sections are all available in the device, but not all of them can be used at the same
time. This does not imply that the device is not fully activated in any given implementation: The CPM
architecture has the advantage of using common hardware resources for many different protocols, and
applications. Two physical factors limit the functionality in any given system—pinout and performance.

1.6.1

Pin Configurations

Some pins have multiple functions. Choosing one function may preclude the use of another. Information
about multiplexing constraints can be found in

Chapter 16, “CPM Multiplexing,

and

Chapter 40,

“Parallel I/O Ports.

1.6.2

Serial Performance

Serial performance depends on a number of factors:

Serial rate versus CPM clock frequency for adequate sampling on serial channels

Serial rate and protocol versus CPM clock frequency for CP protocol handling

Serial rate and protocol versus bus bandwidth

Serial rate and protocol versus system core clock for adequate protocol handling

The second item above is addressed in this section—the CP’s ability to handle high bit-rate protocols in
parallel. Slow bit-rate protocols do not significantly affect those numbers.

Table 1-2

describes a few options to configure the fast communications channels on the PowerQUICC II.

The frequency specified is the minimum CPM frequency necessary to run the mentioned protocols
concurrently at full-duplex.

Table 1-2. Serial Performance

1

1

For all PowerQUICC II devices, except for the MPC8250 (see

Table 1-3

).

FCC1

FCC2

FCC3

2

2

Not on the MPC8255.

MCC

CPM Clock

60x Bus Clock

155-Mbps ATM

100 BaseT

100 BaseT

133 MHz

66 MHz

100 BaseT

100 BaseT

100 BaseT

133 MHz

66 MHz

155-Mbps ATM

128 * 64 Kbps channels

133 MHz

66 MHz

100 BaseT

100 BaseT

128 * 64 Kbps channels

133 MHz

66 MHz

155-Mbps ATM

256 * 64 Kbps channels

166 MHz

66 MHz

100 BaseT

256 * 64 Kbps channels

133 MHz

66 MHz

45-Mbps HDLC

256 * 64 Kbps

133 MHz

66 MHz

45-Mbps HDLC

100 BaseT

256 * 64 Kbps

166 MHz

66 MHz

100 BaseT

16 * 576 Kbps

166 MHz

66 MHz

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