Freescale Semiconductor MPC8260 - Manual (Page 260)

60x Signals
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
7-4 Freescale Semiconductor
a snoop copyback; may also be negated if the external master cancels a bus request
internally before receiving a qualified BG.
High Impedance—Occurs during a hard reset or checkstop condition.
7.2.1.2 Bus Grant (BG)
The address bus grant (BG) signal is both an input and an output signal.
7.2.1.2.1 Bus Grant (BG)—Input
The following are the state meaning and timing comments for the BG signal input.
State Meaning Asserted—Indicates that the PowerQUICC II may, with the proper qualification,
begin a bus transaction and assume ownership of the address bus. A qualified bus
grant is generally determined from the bus state as follows: QBG = BG • ¬ABB
• ¬ARTRY where ARTRY is asserted only during the cycle after AACK. Note that
the assertion of BR is not required for a qualified bus grant (for bus parking).
Negated—Indicates that the PowerQUICC II is not granted next address
ownership.
Timing Comments Assertion—May occur on any cycle. Once the PowerQUICC II has assumed
address bus ownership, it does not begin checking for BG again until the cycle
after AACK.
Negation—May occur whenever the PowerQUICC II must be prevented from
using the address bus. The PowerQUICC II may still assume address bus
ownership on the cycle BG is negated if it was asserted the previous cycle with
other bus grant qualifications.
7.2.1.2.2 Bus Grant (BG)—Output
Following are the state meaning and timing comments for the BG signal output.
State Meaning Asserted—Indicates that the external device may, with the proper qualification,
begin a bus transaction and assume ownership of the address bus. A qualified bus
grant is generally determined from the bus state as follows: QBG = BG • ¬ABB
• ¬ARTRY where ARTRY is asserted only during the cycle after AACK. Note that
the assertion of BR is not required for a qualified bus grant (for bus parking).
Negated—Indicates that the external device is not granted next address
ownership.
Timing Comments Assertion—May occur on any cycle. Once the external device has assumed
address bus ownership, it does not begin checking for BG again until the cycle
after AACK.
Negation—May occur when an external device must be kept from using the
address bus. The external device may still assume address bus ownership on the
cycle that BG is negated if it was asserted the previous cycle with other bus grant
qualifications.