10 outgoing cas status register (ocassr), Table 31-9. ocassr field descriptions, Outgoing cas status register (ocassr) -35 – Freescale Semiconductor MPC8260 User Manual

Page 1051: Ocassr field descriptions -35, Section 31.10, “outgoing cas status, Register (ocassr)

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ATM AAL1 Circuit Emulation Service

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2

Freescale Semiconductor

31-35

31.10 Outgoing CAS Status Register (OCASSR)

Figure 31-25

shows the layout of the outgoing CAS block status register (OCASSR).

This status register contains sticky bits that give the software application an indication that the CP has
modified the associated CAS block. When the ATM receiver operates in core CAS modify mode
RCT[CCASM=1], the CP generates an interrupt and sets the appropriate sticky bit in OCASSR each time
an AAL1 cell is received with new signaling information (one or more signaling nibble has changed).

Note that this flag bit stays set until it is cleared by software. If new signaling is received and the relevant
sticky bit is already set, the CP updates the CAS block without generating another interrupt.

Table 31-9

describes OCASSR fields.

0x14

0–3

ICASB/SRT

S_TMP

ICASB applies when in CAS mode. Incoming CAS Block. Points to one of the eight
available internal CAS block. The starting address of the table is
IN_CAS_BLOCK_BASE+ICASB

× 32. See

Section 31.4.7.1, “CAS Routing Table

” for

more details.
Note that the RCT and TCT use the same CAS routing table (CRT).

SRTS_TMP applies when not in CAS mode. Before a cell with SN = 1 is sent, the CP
reads the SRTS code from external SRTS logic, writes it to SRTS_TMP, and then
inserts SRTS_TMP into the next four cells with an odd SN.

4–15

SP

Structured pointer. Used by the CP to calculate the structured pointer. Initialize to 0.
Structured format only.

0

7

8

9

10

11

12

13

14

15

Field

MCASB7 MCASB6 MCASB5 MCASB4 MCASB3 MCASB2 MCASB1 MCASB0

Figure 31-25. Outgoing CAS Status Register (OCASSR)

Table 31-9. OCASSR

Field Descriptions

Bits

Name

Description

0–7

Reserved, should be cleared during initialization.

8, 9,

10, 11,
12, 13,

14, 15

MCASB

n

Modify CAS Block

n

.

When the CP updates this outgoing CAS block, it sets the MCASB

n

sticky bit and generates an

interrupt to notify the core that the signaling information has changed in block

n

. Each channel

selects the CAS block number in its RCT; see

Section 31.9.1.1, “AAL1 CES Protocol-Specific RCT

.”

Table 31-8. AAL1 CES Protocol-Specific TCT Field Descriptions (continued)

Offset

Bits

Name

Description

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