Freescale Semiconductor MPC8260 - Manual (Page 568)

Communications Processor Module Overview
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
14-20 Freescale Semiconductor
unused parameter RAM, such as, in the area made available when a peripheral controller or sub-block is
not being used.
Microcode can be executed from the first 12 Kbytes. To ensure an uninterrupted instruction stream (one
per cycle), no other agent is allowed to use a RAM bank used by the microcode. Since the first 12 Kbytes
are divided to six 2-Kbyte banks, RAM microcode occupies 2, 4, 6, 8, 10, or 12 Kbytes of RAM,
depending on RCCR[ERAM]; see
Section 14.3.7, “RISC Controller Configuration Register (RCCR).”
14.5.1 Buffer Descriptors (BDs)
The peripheral controllers (FCCs, SCCs, SMCs, MCCs, SPI, and I 2 C) always use BDs for controlling
buffers and their BD formats are all the same, as shown in Table 14-9 .
If the IDMA is used in the buffer chaining or auto-buffer mode, the IDMA channel also uses BDs. They
are described in
Section 19.3, “IDMA Emulation.”
NOTE
The CPM accesses BDs by initiating a DMA cycle on either the 60x or local
bus. If BDs are located in DPRAM, the CPM initiates a cycle on the 60x bus
because DPRAM is a slave device on the 60x bus. Therefore, a system
design should not plan to access the 60x bus simultaneously with DPRAM
BD fetches.
14.5.2 Parameter RAM
The CPM maintains a section of RAM called the parameter RAM, which contains many parameters for
the operation of the FCCs, SCCs, SMCs, SPI, I
2 C, and IDMA channels. An overview of the parameter
RAM structure is shown in Table 14-10 .
The exact definition of the parameter RAM is contained in each protocol subsection describing a device
that uses a parameter RAM. For example, the Ethernet parameter RAM is defined differently in some
locations from the HDLC-specific parameter RAM.
Table 14-9. Buffer Descriptor Format
Address Descriptor
Offset + 0 Status and control
Offset + 2 Data length
Offset + 4 High-order buffer pointer
Offset + 6 Low-order buffer pointer