Freescale Semiconductor MPC8260 - Manual (Page 102)

Overview
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
1-8 Freescale Semiconductor
The G2 core has an internal common on-chip (COP) debug processor. This processor allows access to
internal scan chains for debugging purposes. It is also used as a serial connection to the core for emulator
support.
The G2 core performance for the SPEC 95 benchmark for integer operations ranges between 4.4 and 5.1
at 200 MHz. In Dhrystone 2.1 MIPS, the G2 core is 280 MIPS at 200 MHz (compared to 86 MIPS of the
MPC860 at 66 MHz).
The G2 core can be disabled. In this mode, the PowerQUICC II functions as a slave peripheral to an
external core or to another PowerQUICC II device with its core enabled.
1.2.2 System Interface Unit (SIU)
The SIU consists of the following:
• A 60x-compatible parallel system bus configurable to 64-bit data width. The PowerQUICC II
supports 64-, 32-, 16-, and 8-bit port sizes. The PowerQUICC II internal arbiter arbitrates between
internal components that can access the bus (system core, PCI bridge (MPC8250, MPC8265, and
MPC8266 only), CPM, and one external master). This arbiter can be disabled, and an external
arbiter can be used if necessary.
• A local (32-bit data, 32-bit internal and 18-bit external address) bus. This bus is used to enhance
the operation of the very high-speed communication controllers. Without requiring extensive
manipulation by the core, the bus can be used to store connection tables for ATM or buffer
descriptors (BDs) for the communication channels or raw data that is transmitted between
channels. The local bus is synchronous to the 60x bus and runs at the same frequency.
• The local bus can be configured as a 32-bit data and up to 66 MHz PCI (version 2.1) bus
(MPC8250, MPC8265, and MPC8266 only). In PCI mode the bus can be programmed as a host or
as an agent. The PCI bus can be configured to run synchronously or asynchronously to the 60x bus.
The PowerQUICC II has an internal PCI bridge with an efficient 60x-to-PCI DMA for memory
block transfers.
• Applications that require both the local bus and PCI bus need to connect an external PCI bridge
(MPC8250, MPC8265, and MPC8266 only).
• Memory controller supporting 12 memory banks that can be allocated for either the system or the
local bus. The memory controller is an enhanced version of the MPC860 memory controller. It
supports three user-programmable machines. Besides all MPC860 features, the memory controller
also supports SDRAM with page mode and address data pipeline.
• Supports JTAG controller IEEE 1149.1 test access port (TAP).
• A bus monitor that prevents 60x bus lock-ups, a real-time clock, a periodic interrupt timer, and
other system functions useful in embedded applications.
• Glueless interface to L2 cache (MPC2605) and 4-/16-K-entry CAM
(MCM69C232/MCM69C432).