Freescale Semiconductor MPC8260 - Manual (Page 607)

Serial Interface with Time-Slot Assigner
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 15-31
The GCI bus consists of four lines—two data lines, a clock, and a frame synchronization line. Usually, an
8-kHz frame structure defines the various channels within the 256-kbps data rate. The PowerQUICC II
supports two (limited by the number of SMCs) independent GCI buses, each with independent receive and
transmit sections. The interface can also be used in a multiplexed frame structure on which up to eight
physical layer devices multiplex their GCI channels. In this mode, the data rate would be 2,048 kbps.
In the GCI bus, the clock rate is twice the data rate. The SI divides the input clock by two to produce the
data clock. The PowerQUICC II also has data strobe lines and the 1
× data rate clock L1CLKOx output
pins. These signals are used for interfacing devices to GCI that do not support the GCI bus. Table 15-11
describes GCI signals for each transmit and receive channel.
The GCI bus signals are shown in Figure 15-24 .
Figure 15-24. GCI Bus Signals
In addition to the 144-Kbps ISDN 2B+D channels, the GCI provides five channels for maintenance and
control functions:
• B1 is a 64-Kbps bearer channel
• B2 is a 64-Kbps bearer channel
Table 15-11. GCI Signals
Signal Description
L1RSYNC x Used as a GCI sync signal; input to the PowerQUICC II. This signal indicates that the clock periods
following the pulse designate the GCI frame.
L1RCLK x Used as a GCI clock; input to the PowerQUICC II. The L1RCLK x signal frequency is twice the data
clock.
L1RXD x Used as a GCI receive data; input to the PowerQUICC II.
L1TXD x Used as a GCI transmit data; open-drain output. Valid only for the bits that are supported by the IDL;
otherwise, three-stated.
L1CLKO x Optional signal; output from the PowerQUICC II. This 1
× clock output is used to clock devices that do
not interface directly to the GCI. If the double-speed clock is used, (DSC x bit is set in the SI x MR), this
output is the L1RCLK x divided by 2; otherwise, it is simply a 1 × output of the L1RCLKx signal.
Note: x = a, b, c, and d for TDMa, TDMb, TDMc, and TDMd (for SI1 and SI2).
L1CLK
L1SYNC
L1RXD
L1TXD
B1 B2
B1 B2 M (Monitor) C/I A E
M (Monitor) C/I A E
(2X the data rate)
Notes: Clock is not to scale.
L1CLKO is not shown.
D2 D1
D1 D2