Freescale Semiconductor MPC8260 - Manual (Page 272)

60x Signals
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
7-16 Freescale Semiconductor
Negation—Occurs after the clock cycle of the final (or only) data beat of the
transfer. For a burst transfer, TA may be negated between beats to insert one or
more wait states before the completion of the next beat.
7.2.8.2 Transfer Error Acknowledge (TEA)
The transfer error acknowledge (TEA) signal is both input and output on the PowerQUICC II.
7.2.8.2.1 Transfer Error Acknowledge (TEA)—Input
Following are the state meaning and timing comments for the TEA input signal.
State Meaning Asserted—Indicates that a bus error occurred. The assertion of TEA causes the
negation/high impedance of DBB in the next clock cycle. However, data entering
the PowerQUICC II internal memory resources such as GPRs or caches are not
invalidated.
Negated—Indicates that no bus error was detected.
Timing Comments Assertion—May be asserted while DBB is asserted and for the cycle after is TA is
asserted during a read operation. TEA should be asserted for one cycle only.
Negation—TEA must be negated no later than the negation of DBB.
7.2.8.2.2 Transfer Error Acknowledge (TEA)—Output
Following are the state meaning and timing comments for the TEA output.
State Meaning Asserted—Indicates that a bus error has occurred. Assertion of TEA terminates
the transaction in progress; that is, asserting TA is unnecessary because it is
ignored by the target device. An unsupported memory transaction, such as a
direct-store access or a graphics read or write, causes the assertion of TEA
(provided TEA is enabled and the address transfer matches the PowerQUICC II
memory map).
Negated—Indicates that no bus error was detected.
Timing Comments Assertion—Occurs on the first clock after the bus error is detected.
Negation—Occurs one clock after assertion.
7.2.8.3 Partial Data Valid Indication (PSDVAL)
The partial data valid indication (PSDVAL) is both an input and output on the PowerQUICC II.
7.2.8.3.1 Partial Data Valid (PSDVAL)—Input
Following are the state meaning and timing comments for the PSDVAL input signal. Note that TA asserts
with PSDVAL to indicate the termination of the current transfer and for each complete data beat in burst
transactions.
State Meaning Asserted—Indicates that a beat data transfer completed successfully. Note that
PSDVAL must be asserted for each data beat in a single beat, port size and burst