Freescale Semiconductor MPC8260 - Manual (Page 1260)

Serial Peripheral Interface (SPI)
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
38-14 Freescale Semiconductor
— For a TxBD, this is the number of octets the CP should transmit from its buffer. Normally, this
value should be greater than zero. If the character length is more than 8 bits, the data length
should be even. For example, to send three characters of 8-bit data, 1 start, and 1 stop, the data
length field should be initialized to 3. However, to send three characters of 9-bit data, the data
length field should be initialized to 6 since the three 9-bit data fields occupy three half-words
in memory. The CP never modifies this field.
• The word at offset + 4 points to the beginning of the buffer.
— For an RxBD, the pointer must be even and can point to internal or external memory.
— For a TxBD, the pointer can be even or odd, unless the character exceeds 8 bits, for which it
must be even. The buffer can be in internal or external memory.
38.7.1.1 SPI Receive BD (RxBD)
The CP uses RxBDs to report on each received buffer. It closes the current buffer, generates a maskable
interrupt, and starts receiving data in the next buffer once the current buffer is full. The CP also closes the
buffer when the SPI is configured as a slave and SPISEL is negated, indicating that reception stopped. The
core should write RxBD bits before the SPI is enabled. The format of an RxBD is shown in
Figure 38-11 .
Table 38-8 describes the RxBD status and control fields.
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Offset + 0 E — W I L — CM — OV ME
Offset + 2 Data Length
Offset + 4 Rx Buffer Pointer
Offset + 6
Figure 38-11. SPI RxBD
Table 38-8. SPI RxBD Status and Control Field Descriptions
Bits Name Description
0 E Empty.
0 The buffer is full or stopped receiving because of an error. The core can examine or write to any
fields of this RxBD, but the CP does not use this BD while E = 0.
1 The buffer is empty or reception is in progress. The CP owns this RxBD and its buffer. Once E is
set, the core should not write any fields of this RxBD.
1 — Reserved, should be cleared.
2 W Wrap (last BD in table).
0 Not the last BD in the RxBD table.
1 Last BD in the RxBD table. After this buffer is used, the CP receives incoming data using the BD
pointed to by RBASE (top of the table). The number of BDs in this table is determined only by the
W bit and overall space constraints of the dual-port RAM.
3 I Interrupt.
0 No interrupt is generated after this buffer is filled.
1 SPIE[RXB] is set when this buffer is full, indicating the need for the core to process the buffer.
SPIE[RXB] causes an interrupt if not masked.