Freescale Semiconductor MPC8260 - Manual (Page 322)

PCI Bridge
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
9-16 Freescale Semiconductor
the AD lines, reaches a stable value. This means that a valid address and command are driven on the AD
and PCI_C/BE lines one cycle before the assertion of FRAME.
For Type 1 translations, the PCI bridge copies the contents of the CONFIG_ADDR register directly onto
the PCI address/data lines during the address phase of a configuration cycle, with the exception that
AD[1-0] contains 0b01 (not 0b00 as in Type 0 translations).
NOTE
Due to design constraints, the software must write a value to the
CONFIG_ADDR register prior to each access to the CONFIG_DATA
register, even if the address was not changed.
When the PowerQUICC II is configured as a host device, it sometimes needs to perform configuration
reads from unpopulated PCI slots (as part of the system configuration). To avoid getting a machine check
interrupt, the following steps should be taken:
1. Mask the “PCI No response” bit in the error mask register (clear bit 3). Refer to Section 9.11.1.9,
“Error Status Register (ESR).”
2. Make the PCI configuration reads.
3. Clear bit 3 in the error status register (by writing 0x08).
4. Unmask (write'1') bit 3 in the error mask register. Refer to Section 9.11.1.10, “Error Mask Register
(EMR).”
9.9.1.4.5 Agent Mode Configuration Access
When the PCI bridge is configured as an agent device, it responds to remote host generated PCI
configuration accesses to the PCI interface. This is indicated by decoding the configuration command
along with the PCI bridge's IDSEL being asserted. A remote host can access the 256-byte PCI
configuration area (
Figure 9-32 ) and the memory-mapped configuration registers within the PCI bridge.
9.9.1.4.6 Special Cycle Command
A special cycle command contains no explicit destination address but is broadcast to all PCI agents. Each
receiving agent must determine whether the message is applicable to itself. No assertion of DEVSEL in
response to a special cycle command is necessary.
A special cycle command is like any other bus command in that it has an address phase and a data phase.
The address phase starts like all other commands with the assertion of FRAME and completes when
FRAME and IRDY are negated. Special cycles terminate with a master-abort. (In the special cycle case,
the received-master-abort bit in the configuration status register is not set.)
The address phase contains no valid information other than the command field. Even though there is no
explicit address, the address/data lines are driven to a stable state and parity is generated. During the data
phase, the address/data lines contain the message type and an optional data field. The message is encoded
on the sixteen least-significant bits (AD[15-0]). The data field is encoded on AD[31-16]. When running a
special cycle, the PCI bridge can insert wait states, but because no specific target is addressed, the message
and data are valid on the first clock IRDY is asserted.