Freescale Semiconductor MPC8260 - Manual (Page 394)

PCI Bridge
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
9-88 Freescale Semiconductor
60x bus, or when no data is left to transfer. Reading from PCI memory and writing to 60x memory
can occur concurrently.
• 60x-memory-to-PCI-memory transfers—The DMA controller initially fetches data from 60x
memory into the DMA queue. As soon as the first data arrives into the queue, the DMA engine
initiates write transactions to PCI memory. The DMA controller stops the transfer either when
there is an error on the PCI bus or 60x bus, or there is no more data left to transfer. Reading from
60x memory and writing to PCI memory can occur concurrently.
• 60x-memory-to-60x-memory transfers—The DMA controller begins reading data from 60x
memory and storing it in the DMA queue. Once sufficient data is stored in the queue, the DMA
controller begins writing data to 60x memory space beginning at the destination address. The
process is repeated until there is no more data to transfer or an error condition has occurred while
accessing memory.
9.13.1.6 DMA Registers
Each DMA channel has a set of seven 32-bit registers (mode, status, current descriptor address, next
descriptor address, source address, destination address, and byte count) to support transactions. This
section describes the format of the DMA support registers.
9.13.1.6.1 DMA Mode Register [0–3] (DMAMR x )
The mode register allows software to start the DMA transfer and to control various DMA transfer
characteristics.
Figure 9-82. DMA Mode Register [0–3] (DMAMR x)
Table 9-66 describes DMAMRx fields.
31 24 23 21 20 19 18 17 16
Field — BWC DM_SEN IRQS — DAHTS
Reset 0000_0000_0000_0000
R/W R/W
Addr 0x10502 (DMAMR0); 0x10582 (DMAMR1); 0x10602 (DMAMR2); 0x10682 (DMAMR3)
15 14 13 12 11 10 9 8 7 6 4 3 2 1 0
Field SAHTS DAHE SAHE PRC — EOTIE — TEM CTM CC CS
Reset 0000_0000_0000_0000
R/W R/W
Addr 0x10500 (DMAMR0); 0x10580 (DMAMR1); 0x10600 (DMAMR2); 0x10680 (DMAMR3)