Freescale Semiconductor MPC8260 - Manual (Page 305)

The 60x Bus
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 8-31
snooping condition). No snoop update to the PowerQUICC II processor cache occurs if the transaction is
not marked global. This includes invalidation cycles.
When the PowerQUICC II processor detects a qualified snoop condition, the address associated with the
TS is compared against the data cache tags. Snooping completes if no hit is detected. However, if the
address hits in the cache, the PowerQUICC II processor reacts according to the MEI protocol shown in
Figure 8-12 . This figure assumes that WIM = 0b001 (memory space is marked for write-back,
caching-allowed, and coherency-enforced modes).
Figure 8-12. MEI Cache Coherency Protocol—State Diagram (WIM = 001)
8.7 Processor State Signals
This section describes the PowerQUICC II’s support for atomic update and memory through the use of the
lwarx/stwcx. instruction pair. It also describes the TLBISYNC input.
Invalid
Modified
WH
SH
SH/CRW
WM
WH
RH
SH = Snoop hit
RH = Read hit
WH = Write hit
WM = Write miss
RM = Read miss
SH/CRW = Snoop hit, cacheable read/write
SH/CIR = Snoop hit, cache-inhibited read
= Snoop push
= Cache line fill
Exclusive
SH/CRW
RM
SH/CIR
RH