Freescale Semiconductor MPC8260 - Manual (Page 1014)

ATM Controller and AAL0, AAL1, and AAL5
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
30-94 Freescale Semiconductor
30.15 SRTS Generation and Clock Recovery Using External Logic
The PowerQUICC II supports SRTS generation using external logic. If SRTS generation is enabled
(TCT[SRT] = 1), the PowerQUICC II reads SRTS[0–3] from the external SRTS logic and inserts it into 4
cells whose SN fields equal 1, 3, 5, and 7, as shown in
Figure 30-64 .
Figure 30-64. AAL1 CES SRTS Generation Using External Logic
For every eight cells, the external SRTS logic should supply a valid SRTS code. The CP reads the SRTS
code from the bus selected in TCT[BIB] using a DMA read cycle of 1-byte data size. Each AAL1 CES
channel can be programmed to select one of 16 addresses available for reading the SRTS result. The SRTS
code should be placed on the least-significant nibble of that address (SRTS[0]=lsb, SRTS[3]=msb). The
SRTS is synchronized with the sequence count cycle—SRTS[0] is inserted into the cell with SN = 7;
SRTS[3] is inserted into the cell with SN = 1. For every eighth AAL1 CES SAR PDU, the SRTS logic
Table 30-50. COMM_INFO Field Descriptions
Offset Bits Name Description
0x86 0–4 — Reserved, should be cleared.
5 CTB Connection tables bus. Used for external channels only
0 External connection tables reside on the 60x bus.
1 External connection tables reside on the local bus.
6–10 PHY# PHY number. In single PHY mode this field should be cleared In multiple PHY mode this
field is an index to the APC parameter table associated with this channel.
11–12 ACT ATM channel type
00 Other channel
01 VBR channel
1x Reserved
13-15 PRI APC priority level.
000 Highest priority (APC_LEVEL1)
111 Lowest priority (APC_LEVEL8).
0x88 0-15 CC Channel code. The channel code associated with the current channel.
0x8A 0-15 BT Burst tolerance. For use by VBR channels only (ACT field is 0b01). Specifies the initial
burst tolerance (GCRA burst credit) of the current VC.
p = 4 bit counter 1/64
155.52 MHz
2.43 MHz (E1/T1)
Latch
fs
Counter
divided by N
(N=3008 bits = 8 SAR PDU)
SRTS
External SRTS Logic
SN=1 SN=3 SN=5 SN=7
DMA reads new SRTS code