Freescale Semiconductor MPC8260 - Manual (Page 301)

The 60x Bus
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 8-27
Figure 8-8 shows both a single-beat and burst data transfer. The PowerQUICC II asserts TA to mark the
cycle in which data is accepted. In a normal burst transfer, the fourth assertion of TA signals the end of a
transfer.
Figure 8-8. Single-Beat and Burst Data Transfers
8.5.4 Effect of ARTRY Assertion on Data Transfer and Arbitration
The PowerQUICC II allows an address tenure to overlap its associated data tenure. The PowerQUICC II
internally guarantees that the first TA of the data tenure is delayed to be at the same time or after the
ARTRY window (the clock after the assertion of AACK).
8.5.5 Port Size Data Bus Transfers and PSDVAL Termination
The PowerQUICC II can transfer data via data ports of 8, 16, 32, and 64 bits, as shown in Section 8.4.3,
“Address Transfer Attribute Signals.” Single-beat transaction sizes can be 8, 16, 32, 64, 128, and 192 bits;
burst transactions are 256 bits. Single-beat and burst transactions are divided into to a number of
intermediate beats depending on the port size. The PowerQUICC II asserts PSDVAL to mark the cycle in
which data is accepted. Assertion of PSDVAL in conjunction with TA marks the end of the transfer in
single-beat mode. The fourth assertion of PSDVAL in conjunction with TA signals the end of a burst
transfer.
Figure 8-9 shows an extended transaction of 4 words to a port size of 32 bits. The single-beat
transaction is translated to four port-sized beats.
CLKOUT
ADDR + ATTR
TS
AACK
DBG
TA
D[0–63]
PSDVAL
D0 D1 D2 D3