Freescale Semiconductor MPC8260 - Manual (Page 702)

Serial Communications Controllers (SCCs)
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
20-24 Freescale Semiconductor
If the DPLL is not needed, NRZ or NRZI codings can be selected in GSMR_L[RENC, TENC]. Coding
definitions are shown in
Table 20-9 .
20.3.7 Reconfiguring the SCCs
The proper reconfiguration sequence must be followed for SCC parameters that cannot be changed
dynamically. For instance, the internal baud rate generators allow on-the-fly changes, but the
DPLL-related GSMR does not. The steps in the following sections show how to disable, reconfigure and
re-enable an SCC to ensure that buffers currently in use are properly closed before reconfiguring the SCC
and that subsequent data goes to or from new buffers according to the new configuration.
Modifying parameter RAM does not require the SCC to be fully disabled. See the parameter RAM
description for when values can be changed. To disable all peripheral controllers, set CPCR[RST] to reset
the entire CPM.
20.3.7.1 General Reconfiguration Sequence for an SCC Transmitter
An SCC transmitter can be reconfigured by following these general steps:
1. If the SCC is sending data, issue a STOP TRANSMIT command. Transmission should stop smoothly.
If the SCC is not transmitting (no TxBDs are ready or the GRACEFUL STOP TRANSMIT command
has been issued and completed) or the INIT TX PARAMETERS command is issued, the STOP
TRANSMIT command is not required.
2. Clear GSMR_L[ENT] to disable the SCC transmitter and put it in reset state.
3. Modify SCC Tx parameters or parameter RAM. To switch protocols or restore the initial Tx
parameters, issue an INIT TX PARAMETERS command.
Table 20-9. DPLL Codings
Coding Description
NRZ A one is represented by a high level for the duration of the bit and a zero is represented by a low level.
NRZI Mark A one is represented by no transition at all. A zero is represented by a transition at the beginning of the
bit (the level present in the preceding bit is reversed).
NRZI
Space A one is represented by a transition at the beginning of the bit (the level present in the preceding bit is
reversed). A zero is represented by no transition at all.
FM0 A one is represented by a transition only at the beginning of the bit. A zero is represented by a transition
at the beginning of the bit and another transition at the center of the bit.
FM1 A one is represented by a transition at the beginning of the bit and another transition at the center of the
bit. A zero is represented by a transition only at the beginning of the bit.
Manchester A one is represented by a high-to-low transition at the center of the bit. A zero is represented by a low to
high transition at the center of the bit. In both cases there may be a transition at the beginning of the bit
to set up the level required to make the correct center transition.
Differential
Manchester A one is represented by a transition at the center of the bit with the opposite direction from the transition
at the center of the preceding bit. A zero is represented by a transition at the center of the bit with the
same polarity from the transition at the center of the preceding bit.