Figure 19-8. idmax channel’s bd table, 2 idmax parameter ram, Idmax parameter ram -17 – Freescale Semiconductor MPC8260 User Manual

Page 661: Idmax channel’s bd table -17, 2 idma, Parameter ram

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SDMA Channels and IDMA Emulation

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2

Freescale Semiconductor

19-17

Figure 19-8. IDMA

x Channel’s BD Table

Data associated with each IDMA channel is stored in buffers and each buffer is referenced by a BD that
uses a circular table structure in the dual-port RAM. Control options such as interrupt and DONE assertion
are also programmed on a per-buffer basis in each BD.

Data may be transferred in the two following modes:

Auto buffer mode. The IDMA continuously transfers data to/from the location programmed in the
BD until a

STOP

_

IDMA

command is issued or DONE is asserted externally.

Buffer chaining mode. Data is transferred according to the first BD parameters, then the second BD
and so forth. The first BD is reused (if ready) until the BD with the last bit set is reached. IDMA
transfers stop and restarts when the BD table is reinitialized and a

START

_

IDMA

command is issued.

19.8.2

IDMA

x

Parameter RAM

When an IDMAx channel is configured to auto buffer or buffer chaining mode, the PowerQUICC II uses
the IDMAx parameters listed in the

Table 19-4

. Parameters should be modified only while the channel is

disabled, that is, before the first

START

_

IDMA

command or when the event register’s stop-completed bit

(IDSR[SC]) is set following a

STOP

_

IDMA

command.

Each IDMAx channel parameter table can be placed at any 64-byte aligned address in the dual-port RAM’s
general-purpose area (banks 1–8, 11 and 12). The CP accesses each IDMAx channel parameter table using
a user-programmed pointer (IDMAx_BASE) located in the parameter RAM; see

Section 14.5.2,

“Parameter RAM.”

For example, if the IDMA1 channel parameter table is to be placed at address offset

0x2000 in the dual-port RAM, write 0x2000 to IDMA1_BASE.

IDMA

x

BD Base

Address (IBASE)

Source Device or

Buffer 0

Source Device or

Buffer 1

Source Device or

Buffer 2

Source Device or

Buffer

n

BD 0

Destination Device or

Buffer 0

BD 1

BD 2

BD

n

Destination Device or

Buffer 1

Destination Device or

Buffer 2

Destination Device or

Buffer

n

••

••

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