Freescale Semiconductor MPC8260 - Manual (Page 229)

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MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 5-7
The configuration words for all PowerQUICC IIs are assumed to reside in an EPROM connected to CS0
of the configuration master. Because the port size of this EPROM is not known to the configuration master,
before reading the configuration words, the configuration master reads all configuration words
byte-by-byte only from locations that are independent of port size.
Table 5-6. shows addresses that should be used to configure the various PowerQUICC IIs. Byte addresses
that do not appear in this table have no effect on the configuration of the PowerQUICC II chips. The values
of the bytes in
Table 5-6 are always read on byte lane D[0–7] regardless of the port size
.
The configuration master first reads a value from address 0x00 then reads a value from addresses 0x08,
0x10, and 0x18. These four bytes are used to form the configuration word of the configuration master,
which then proceeds reading the bytes that form the configuration word of the first slave device. The
configuration master drives the whole configuration word on D[0–31] and toggles its A0 address line.
Each configuration slave uses its RSTCONF input as a strobe for latching the configuration word during
HRESET assertion time. Thus, the first configuration slave whose RSTCONF input is connected to
configuration master’s A0 output latches the word driven on D[0–31] as its configuration word. In this way
the configuration master continues to configure all PowerQUICC II chips in the system. The configuration
master always reads eight configuration words regardless of the number of PowerQUICC II parts in the
system. In a simple system that uses one stand-alone PowerQUICC II, it is possible to use the default hard
reset configuration word (all zeros). This is done by tying RSTCONF input to VCC. Another scenario may
be a system which has no boot EPROM. In this case the user can configure the PowerQUICC II as a
configuration slave by driving RSTCONF to 1 during PORESET assertion and then applying a negative
pulse on RSTCONF and an appropriate configuration word on D[0–31]. In such a system, asserting
HRESET in the middle of operation causes the PowerQUICC II to return to the configuration programmed
after PORESET assertion (not the default configuration represented by configuration word of all zeros).
Sixth configuration slave A5
Seventh configuration slave A6
Table 5-6. Configuration EPROM Addresses
Configured Device Byte 0 Address Byte 1 Address Byte 2 Address Byte 3 Address
Configuration master 0x00 0x08 0x10 0x18
First configuration slave 0x20 0x28 0x30 0x38
Second configuration slave 0x40 0x48 0x50 0x58
Third configuration slave 0x60 0x68 0x70 0x78
Fourth configuration slave 0x80 0x88 0x90 0x98
Fifth configuration slave 0xA0 0xA8 0xB0 0xB8
Sixth configuration slave 0xC0 0xC8 0xD0 0xD8
Seventh configuration slave 0xE0 0xE8 0xF0 0xF8
Table 5-5. RSTCONF Connections in Multiple-PowerQUICC II Systems (continued)
Configured Device RSTCONF Connection