Freescale Semiconductor MPC8260 - Manual (Page 1013)

ATM Controller and AAL0, AAL1, and AAL5
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 30-93
Example:
Suppose the PowerQUICC II is connected to four 155 Mbps PHY devices and the maximum transmission
rate is 155 Mbps for the first PHY and 10 Mbps for the rest of the PHYs. The BRG CLK should be set
according to the highest rate. If the CPM clock is 133 MHz and the BRG CLK is 66 MHz, the BRG should
be programmed to divide the CPM clock by 181 to generate cell transmit requests every 362 system clocks:
For the 155 Mbps PHY, the FTIRR divider should be programmed to zero (the BRG CLK is divided by
one); for the rest of the 10 Mbps PHYs, the FTIRR divider should be programmed to 14 (the BRG CLK
is divided by 15).
See also Section 30.16.1, “Using Transmit Internal Rate Mode.”
30.14 ATM Transmit Command
The CPM command set includes an ATM TRANSMIT that can be sent to the CP command register (CPCR),
described in Section 14.4.1.
The ATM TRANSMIT command (CPCR[opcode] = 0b1010, CPCR[SBC[code]] = 0b01110,
CPCR[SBC[page]] = 0b00100 or 0b00101 (FCC1 or FCC2), CPCR[MCN] = 0b0000_1010) turns a
passive channel into an active channel by inserting it into the APC scheduling table. Note that an
ATM
TRANSMIT command should be issued only after the channel’s TCT is completely initialized and the
channel has BDs ready to transmit. Note also that CPCR[SBC[code]] = 0b01110 and not FCC1 or FCC2
code.
Before issuing the command, the user should initialize COMM_INFO fields in the parameter RAM as
described in
Figure 30-63 .
Table 30-50 describes COMM_INFO fields.
Offset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
0x86 — CTB PHY# ACT PRI
0x88 Channel Code (CC)
0x8A BT
Figure 30-63. COMM_INFO Field
66MHz 53 8
Ч ( ) Ч ( )
155.52Mbps
-------------------------------------------------- 181 =