Freescale Semiconductor MPC8260 - Manual (Page 146)

G2 Core
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
2-28 Freescale Semiconductor
2.8 Differences between the PowerQUICC II’s
G2 Core and the MPC603e Microprocessor
The PowerQUICC II’s processor core is a derivative of the MPC603e microprocessor design. Some
changes have been made and are visible either to a programmer or a system designer. Any software
designed around an MPC603e is functional when replaced with the PowerQUICC II except for the specific
customer-visible changes listed in
Table 2-7 .
Software can distinguish between the MPC603e and the PowerQUICC II by reading the processor version
register (PVR). The PowerQUICC II’s processor version number is 0x0081; the processor revision level
starts at 0x0100 and is incremented for each revision of the chip.
Table 2-7. Major Differences between PowerQUICC II’s G2 Core and the
MPC603e User’s Manual
Description Impact
Added bus multipliers of 4.5x, 5x, 5.5x,
6x, 6.5x 7x, 7.5x, 8x Occupies unused encodings of the PLL_CFG[0–4]
Added hardware support for misaligned
little endian accesses Except for strings/multiples, little-endian load/store accesses not on a word
boundary generate exceptions under the same circumstances as
big-endian accesses.
Removed misalignment support for
eciwx and ecowx instructions. These instructions take an alignment exception if not on a word boundary.
Added ability to broadcast dcbf, dcbi,
and dcbst onto the 60x bus Setting HID0[ABE] enables the new broadcast feature (new in the
PID7v-603e). The default is to not broadcast these operations.
Added ability to reflect the value of the M
bit onto the 60x bus during instruction
translations Setting HID0[IFEM] enables this feature. The default is to not present the M
bit on the bus.
Removed HID0[EICE] There is no support for ICE pipeline tracking.
Added instruction and data cache
locking mechanism Implements a cache way locking mechanism for both the instruction and
data caches. One to three of the four ways in the cache can be locked with
control bits in the HID2 register. See
Section 2.3.1.2.3, “Hardware
Implementation-Dependent Register 2 (HID2).”
Added pin-configurable reset vector The value of MSR[IP], interrupt prefix, is determined at hard reset by the
hardware configuration word.
Addition of speed-for-power functionality The processor core implements an additional dynamic power management
mechanism. HID2[SFP] controls this function. See Section 2.3.1.2.3,
“Hardware Implementation-Dependent Register 2 (HID2).”
Improved access to cache during block
fills The PowerQUICC II provides quicker access to incoming data and instruc-
tion on a cache block fill. See
Section 2.4.2, “PowerQUICC II Implementa-
tion-Specific Cache Implementation.”
Improved integer divide latency Performance of integer divide operations has been improved in the
processor core. A divide takes half the cycles to execute as described in
MPC603e User’s Manual . The new latency is reflected in Table 2-6 .