Freescale Semiconductor MPC8260 - Manual (Page 470)

Memory Controller
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
11-52 Freescale Semiconductor
The GPCM allows a glueless and flexible interface between the PowerQUICC II, SRAM, EPROM,
FEPROM, ROM devices, and external peripherals. The GPCM contains two basic configuration register
groups—BRx and ORx.
Although GPCM does not support bursting, the internal logic will split a burst into individual beats that
the GPCM can support. Therefore, the flash can be cached. Note that if the PowerQUICC II is in 60x-bus
compatible mode, baddr[27–31] should be used instead of a[27–31].
Table 11-30 lists the GPCM interface signals on the 60x and local bus
GPCM-controlled devices can use BCTLx as read/write indicators. The BCTLx signals appears as R/W in
the timing diagrams. See
Section 11.2.7, “Data Buffer Controls (BCTLx and LWR).”
Additional control is available in 60x-compatible mode (60x bus only)—ALE–external address latch
enable
In this section, the output-enable and write-enable signals are generically labeled OE and WE. When using
the 60x bus they refer to POE and PWE, and for the local bus they refer to LOE and LWE.
Figure 11-40 shows a simple connection between a 32-bit port size SRAM device and the
PowerQUICC II.
Figure 11-40. GPCM-to-SRAM Configuration
Table 11-30. GPCM Interfaces Signals
60x Bus Local Bus Comments
CS[0–11] Device select
PWE[0–7] LWE[0–3] Write enables for write cycles
POE LOE Output enable for read cycles
CE
WE[0–3]
OE
Address
Data
32-Bit Wide SRAM
D[0–31]
A[15–29]
GPL_x1/OE
WE[0–3]
CSx 128K
PowerQUI