Freescale Semiconductor MPC8260 - Manual (Page 1276)

I 2 C Controller
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
39-12 Freescale Semiconductor
Figure 39-12. I
2
C Memory Structure
39.7.1 I 2 C Buffer Descriptors (BDs)
Receive and transmit buffer descriptors report information about each buffer transferred and whether a
maskable interrupt should be generated. Each 64-bit BD, shown in
Figure 39-13 and Figure 39-14 , has the
following structure:
• The half word at offset + 0 contains status and control bits. The CP updates the status bits after the
buffer is sent or received.
• The half word at offset + 2 contains the data length (in bytes) that is sent or received.
— For an RxBD, this is the number of octets the CP writes into this RxBD’s buffer once the
descriptor closes. The CP updates this field after the received data is placed into the associated
buffer. Memory allocated for this buffer should be no smaller than MRBLR.
— For a TxBD, this is the number of octets the CP should transmit from its buffer. Normally, this
value should be greater than zero. The CP never modifies this field.
• The word at offset + 4 points to the beginning of the buffer.
— For an RxBD, the pointer must be even and can point to internal or external memory.
— For a TxBD, the pointer can be even or odd. The buffer can reside in internal or external
memory.
39.7.1.1 I 2 C Receive Buffer Descriptor (RxBD)
Using RxBDs, the CP reports on each buffer received, closes the current buffer, generates a maskable
interrupt, and starts receiving data in the next buffer when the current one is full. It closes the buffer when
a stop or start condition is found on the I
2 C bus or when an overrun error occurs. The core should write
RxBD bits before the I 2 C controller is enabled.
Status and Control
Data Length
Buffer Pointer
Status and Control
Data Length
Buffer Pointer
Tx Buffer
I2C RxBD Table Pointer
(RBASE)
Rx Buffer
Dual-Port RAM External Memory
TxBD Table
RxBD Table
Tx Buffer
I2C TxBD Table Pointer
(TBASE)
I2C RxBD Table
I2C TxBD Table