Freescale Semiconductor MPC8260 - Manual (Page 629)

CPM Multiplexing
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 16-19
16.4.6 CMX SMC Clock Route Register (CMXSMR)
The CMX SMC clock route register (CMXSMR), shown in Figure 16-12 , defines the connection of the
SMCs to the TSA and to the clock sources from the bank of clocks.
Table 16-7 describes CMXSMR fields.
26–28 RS4CS Receive SCC4 clock source (NMSI mode). Ignored if SCC4 is connected to the TSA (SC4 = 1).
000 SCC4 receive clock is BRG1.
001 SCC4 receive clock is BRG2.
010 SCC4 receive clock is BRG3.
011 SCC4 receive clock is BRG4.
100 SCC4 receive clock is CLK5.
101 SCC4 receive clock is CLK6.
110 SCC4 receive clock is CLK7.
111 SCC4 receive clock is CLK8
29–31 TS4CS Transmit SCC4 clock source (NMSI mode). Ignored if SCC4 is connected to the TSA (SC4 = 1).
000 SCC4 transmit clock is BRG1.
001 SCC4 transmit clock is BRG2.
010 SCC4 transmit clock is BRG3.
011 SCC4 transmit clock is BRG4.
100 SCC4 transmit clock is CLK5.
101 SCC4 transmit clock is CLK6.
110 SCC4 transmit clock is CLK7.
111 SCC4 transmit clock is CLK8
0 1 2 3 4 5 6 7
Field SMC1 — SMC1CS SMC2 — SMC2CS
Reset 0000_0000
R/W R/W
Addr 0x0x11B0C
Figure 16-12. CMX SMC Clock Route Register (CMXSMR)
Table 16-7. CMXSMR Field Descriptions
Bit s Name Description
0 SMC1 SMC1 connection
0 SMC1 is not connected to the TSA and is either connected directly to the NMSIx pins or is not
used. The choice of general-purpose I/O port pins versus SMCn pins is made in the parallel I/O
control register.
1 SMC1 is connected to the TSA of the SIs. The NMSIx pins are available for other purposes.
1 — Reserved, should be cleared
Table 16-6. CMXSCR Field Descriptions (continued)
Bits Name Description