Freescale Semiconductor MPC8260 - Manual (Page 304)

The 60x Bus
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
8-30 Freescale Semiconductor
Figure 8-11. Data Tenure Terminated by Assertion of TEA
The PowerQUICC II interprets the following bus transactions as bus errors:
• Direct-store transactions, as indicated by the assertion of XATS.
• Bus errors asserted by slaves (internal or external).
8.6 Memory Coherency—MEI Protocol
The PowerQUICC II provides dedicated hardware to ensure memory coherency by snooping bus
transactions, by maintaining information about the status of data in a cache block, and by the address retry
capability. Each data cache block includes status bits that support the modified/exclusive/invalid, or MEI,
cache-coherency protocol.
Asserting the global (GBL) output signal indicates whether the current transaction must be snooped by
other snooping devices on the bus. Address bus masters assert GBL to indicate that the current transaction
is a global access (that is, an access to memory shared by more than one device). If GBL is not asserted
for the transaction, that transaction is not snooped. When other devices detect the GBL input asserted, they
must respond by snooping any addresses broadcast. Normally, GBL reflects the M bit value specified for
the memory reference in the corresponding translation descriptor. Care must be taken to minimize the
number of pages marked as global, because the retry protocol discussed in the previous section used to
enforce coherency can require significant bus bandwidth.
When the PowerQUICC II processor is not the address bus master, GBL is an input. The PowerQUICC II
processor snoops a transaction if TS and GBL are asserted together in the same bus clock cycle (a qualified
CLKOUT
ADDR + ATTR
TS
AACK
DBG
TA
Data
TEA
For Single For Burst