Freescale Semiconductor MPC8260 - Manual (Page 519)

Memory Controller
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 11-101
11.8 Handling Devices with Slow or Variable Access Times
The memory controller provides two ways to interface with slave devices that are very slow (access time
is greater than the maximum allowed by the user programming model) or cannot guarantee a predefined
access time (for example some FIFO, hierarchical bus interface, or dual-port memory devices). These
mechanisms are as follows:
• The wait mechanism—Used only in accesses controlled by the UPM. Setting MxMR[GPLx4DIS]
enables this mechanism.
• The external termination (GTA) mechanism is used only in accesses controlled by the GPCM.
ORx[SETA] specifies whether the access is terminated internally or externally.
The following examples show how the two mechanisms work.
11.8.1 Hierarchical Bus Interface Example
Assume that the core initiates a local-bus read cycle that addresses main memory connected to the system
bus. The hierarchical bus interface accepts local bus requests and generates a read cycle on the system bus.
The programmer cannot predict when valid data can be latched by the core because a DMA device may
be occupying the system bus.
• The wait solution (UPM)—The external module asserts UPMWAIT to the memory controller to
indicate that data is not ready. The memory controller synchronized this signal because the wait
signal is asynchronous. As a result of the wait signal being asserted, the UPM enters a freeze mode
at the rising edge of CLKIN upon encountering the WAEN bit being set in the UPM word. The
UPM stays in that state until UPMWAIT is negated. After UPMWAIT is negated, the UPM
continues executing from the next entry to the end of the pattern (LAST bit is set).
• The external termination solution (GPCM)—The bus interface module asserts GTA to the memory
controller when it can sample data. Note that GTA is also synchronized.
11.8.2 Slow Devices Example
Assume that the core initiates a read cycle from a device whose access time exceeds the maximum allowed
by the user programming model.
• The wait solution (UPM)—The core generates a read access from the slow device. The device in
turn asserts the wait signal until the data is ready. The core samples data only after the wait signal
is negated.
• The external termination solution (GPCM)—The core generates a read access from the slow
device, which must generate the asynchronous GTA when it is ready.
11.9 External Master Support (60x-Compatible Mode)
The memory controller supports internal and external bus masters. Accesses from the core or the CPM are
considered internal; accesses from an external bus master are external.
External bus master support is available only if the PowerQUICC II is placed in 60x-compatible mode by
setting BCR[EBM]; see
Section 4.3.2.1, “Bus Configuration Register (BCR).”