Freescale Semiconductor MPC8260 - Manual (Page 811)

SCC AppleTalk Mode
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 26-3
Figure 26-2. Connecting the PowerQUICC II to LocalTalk
The 16
× overspeed of a 3.686-MHz clock can be generated from an external frequency source or from one
of the baud rate generators if the resulting output frequency is close to a multiple of the 3.686 MHz
frequency. The PowerQUICC II asserts RTS throughout the duration of the frame so that RTS can be used
to enable the RS-422 transmit driver.
26.4 Programming the SCC in AppleTalk Mode
The AppleTalk controller is implemented by setting certain bits in the HDLC controller. Otherwise,
Chapter 22, “SCC HDLC Mode,” describes how to program the HDLC controller. Use GSMR, PSMR, or
TODR to program the AppleTalk controller.
26.4.1 Programming the GSMR
Program the GSMR as described below:
1. Set MODE to 0b0010 (AppleTalk).
2. Set DIAG to 0b00 for normal operation, with CD and CTS grounded or configured for parallel I/O.
This causes CD and CTS to be internally asserted to the SCC.
3. Set RDCR and TDCR to (0b10) a 16
× clock.
4. Set the TENC and RENC bits to 0b010 (FM0).
5. Clear TEND for default operation.
6. Set TPP to 0b11 for a preamble pattern of all ones.
7. Set TPL to 0b000 to transmit the next frame with no synchronization sequence and to 001 to
transmit the next frame with the LocalTalk synchronization sequence. For example, data frames do
not require a preceding synchronization sequence. These bits may be modified on-the-fly if the
AppleTalk protocol is selected.
Two HDLC
CRC-16
Flags
Destination
Address
Data
Control
Byte
6-Bit Sync
Sequence
Source
Address
Closing
Flag
16 Ones
(Abort)
RS-422
TXD
RTS
RXD
Stored in Receive Buffer
Standard HDLC frame handling
MINI-DIN 8
Stored in Transmit Buffer
SCC
RTS
TXD
Tx Data
Tx Enable
Rx Data
PowerQUICC II
Connection