Freescale Semiconductor MPC8260 - Manual (Page 1319)

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor Glossary-1
Glossary of Terms and Abbreviations
The glossary contains an alphabetical list of terms, phrases, and abbreviations used in this book.
Some of the terms and definitions included in the glossary are reprinted from IEEE Std. 754-1985,
IEEE Standard for Binary Floating-Point Arithmetic, copyright ©1985 by the Institute of
Electrical and Electronics Engineers, Inc. with the permission of the IEEE.
Note that some terms are defined in the context of how they are used in this book.
A
Architecture. A detailed specification of requirements for a processor or computer
system. It does not specify details of how the processor or computer
system must be implemented; instead it provides a template for a family of
compatible implementations.
Asynchronous exception. Exceptions that are caused by events external to the
processor’s execution. In this document, the term ‘asynchronous
exception’ is used interchangeably with the word interrupt.
Atomic access. A bus access that attempts to be part of a read-write operation to the
same address uninterrupted by any other access to that address (the term
refers to the fact that the transactions are indivisible). The PowerPC
architecture implements atomic accesses through the lwarx/stwcx.
instruction pair.
Autobaud. The process of determining a serial data rate by timing the width of a
single bit.
B
Big-endian. A byte-ordering method in memory where the address n of a word
corresponds to the most-significant byte. In an addressed memory word,
the bytes are ordered (left to right) 0, 1, 2, 3, with 0 being the
most-significant byte. See Little-endian.
Blockage. A pipeline stall that occurs when an instruction occupies an execution
unit and prevents a subsequent instruction from being dispatched.
Boundedly undefined. A characteristic of results of certain operations that are not
rigidly prescribed by the PowerPC architecture. Boundedly- undefined
results for a given operation may vary among implementations, and
between execution attempts in the same implementation.