1 dma direct mode, 2 dma chaining mode, Dma direct mode -86 – Freescale Semiconductor MPC8260 User Manual
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PCI Bridge
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
9-86
Freescale Semiconductor
address. The DMA controller assumes that the source and destination addresses are valid PCI or 60x
memory addresses.
All 60x memory read operations are cache line reads (32 bytes); the DMA controller selects the
appropriate/valid data bytes within the cache line when loading its internal queue. Writing to 60x memory
depends on the alignment of the destination address and the size of the transfer. The DMA controller writes
a full cache line whenever possible. Misaligned destination addresses result in sub-transfers of less than a
cache line on the initial and final beats of the transfer; intermediate beats transfer full cache lines.
Configuring a DMA channel for a transfer size of less than 8 bytes in address hold mode (DAHE or SAHE
is set; refer to
Section 9.13.1.6.1, “DMA Mode Register [0–3] (DMAMRx)”
) precludes cache line writes.
PCI memory read operations depend on the PRC (PCI read command) field in the mode register, the
alignment of the source address and the size of the transfer. The DMA controller attempts to read a full
cache line whenever possible. Writing to PCI memory depends on the alignment of the destination address
and the size of the transfer.
9.13.1.1
DMA Direct Mode
In direct mode, the DMA controller does not read a chain of descriptors from memory but instead uses the
current parameters in the DMA registers to start a DMA transfer. The DMA transfer finishes after all the
bytes specified in the byte count register have been transferred or an error condition has occurred. Below
are the initialization steps of a DMA transfer in direct mode.
•
Poll the CB (channel busy) bit in the status register to make sure the DMA channel is idle (refer to
Section 9.13.1.6.2, “DMA Status Register [0–3] (DMASRx)”
).
•
Initialize the source, destination and byte count register (refer to
Destination Address Register [0–3] (DMADARx),”
Section 9.13.1.6.6, “DMA Byte Count
).
•
Initialize the CTM (channel transfer mode) bit in the mode register (refer to
“DMA Mode Register [0–3] (DMAMRx)”
) to indicate direct mode. Other control parameters in
the mode register can also be initialized here if necessary.
•
First clear then set the CS (channel start) bit in the mode register to start the DMA transfer.
9.13.1.2
DMA Chaining Mode
In chaining mode, the DMA controller loads descriptors from memory prior to a DMA transfer. The DMA
controller begins the transfer according to the descriptor information loaded for each segment. Once the
current segment is finished, the DMA controller reads the next descriptor from memory and begins another
DMA transfer. The process is finished if the current descriptor is the last one in the chain or an error
condition has occurred. Below are the initialization steps of a DMA transfer in chaining mode.
•
Build a chain of descriptor segments in memory. Refer to the
for more information.
•
Poll the CB (channel busy) bit in the status register to make sure the DMA channel is idle.
•
Initialize the current descriptor address register to point to the first descriptor in the chain.
•
Initialize the CTM (channel transfer mode) bit in the mode register to indicate chaining mode.
Other control parameters in the mode register can also be initialized here if necessary.