Freescale Semiconductor MPC8260 - Manual (Page 373)

PCI Bridge
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 9-67
Figure 9-61. Outbound Message Registers (OMR x)
9.12.2 Door Bell Registers
The PCI bridge contains an inbound and an outbound door bell register. The registers are 32-bit. The
inbound door bell allows a remote processor to set a bit in the register from the PCI bus. This, in turn,
causes the PCI bridge to generate an interrupt to the local processor. The local processor can write to the
outbound register which causes the outbound interrupt signal INTA to assert thus interrupting the remote
processor on the PCI bus.
9.12.2.1 Outbound Doorbell Register (ODR)
ODR, described in Figure 9-62 and Table 9-48 , is accessible from the PCI bus and the 60x bus in both host
and agent modes.
31 16
Field OMSG x
Reset Undefined
R/W R/W
Addr 0x1045A (OMR0); 0x1045E (OMR1)
15 0
Field OMSG x
Reset Undefined
R/W R/W
Addr 0x10458 (OMR0); 0x1045C (OMR1)
Table 9-47. OMR x Field Descriptions
Bits Name Description
31–0 OMSG x Outbound message x . Contains generic data to be passed between the local
processor and external hosts.