Freescale Semiconductor MPC8260 - Manual (Page 329)

PCI Bridge
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 9-23
NOTE
When a transaction is performed by a PCI master, the bridge checks the
address against inbound ATUs and if it does not hit, it then checks against
PIMMR; if it is a hit, the bridge translates it to a 60x cycle. Because PIMMR
does not have an associated translation register and window size definition,
the translation is performed as follows: a 128-Kbyte window is provided for
the PCI master to access the PowerQUICC II’s internal (dual port) registers.
It translates to the PowerQUICC II’s IMMR value for the upper bits of the
address. This allows the PCI master to access any of the PCI-bridge registers
without wasting an inbound translation window. In effect, there are a total
of three inbound windows, 2 with ATUs and 1 with PIMMR.
Transactions initiated by the DMA controller or message unit fall into one of the following cases:
• If the transaction address is within one of the outbound PCI translation windows, the transaction is
sent to the PCI bus with address translation.
• If the transaction address is not within a PCI translation window, the transaction is sent to the core
side of the PCI bridge with no address translation.
An address decode flow chart for transactions from the DMA controller or message unit to the PCI bridge
is shown in
Figure 9-13 .
Figure 9-13. Address Decode Flow Chart for Embedded Utilities
(DMA, Message Unit) Mastered Transactions
Example address mappings of these different types of transactions are shown in Figure 9-14 . Note that the
translation mechanism shown is an example only; the address translation, as well as the memory and I/O
destinations, can be programmed independently for each address translation window.
No
Yes
DMA/MU mastered
transaction
Issue transaction
with translated
address to PCI
Issue transaction
with un-translated
address to 60x bus
Hit
Outbound ATU
?