Freescale Semiconductor MPC8260 - Manual (Page 1262)

Serial Peripheral Interface (SPI)
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
38-16 Freescale Semiconductor
38.8 SPI Master Programming Example
The following sequence initializes the SPI to run at a high speed in master mode:
1. Configure port D to enable SPIMISO, SPIMOSI, SPICLK and SPISEL.
2. Configure a parallel I/O signal to operate as the SPI select output signal if needed.
3. In address 0x89FC, assign a pointer to the SPI parameter RAM.
4. Write RBASE and TBASE in the SPI parameter RAM to point to the RxBD and TxBD tables in
the dual-port RAM. Assuming one RxBD followed by one TxBD at the beginning of the dual-port
RAM, write RBASE with 0x0000 and TBASE with 0x0008.
5. Write RFCR and TFCR with 0x10 for normal operation.
6. Write MRBLR with the maximum number of bytes per Rx buffer. For this case, assume 16 bytes,
so MRBLR = 0x0010.
7. Initialize the RxBD. Assume the Rx buffer is at 0x0000_1000 in main memory. Write 0xB000 to
RxBD[Status and Control], 0x0000 to RxBD[Data Length] (optional), and 0x0000_1000 to
RxBD[Buffer Pointer].
2 W Wrap (last BD in TxBD table).
0 Not the last BD in the table.
1 Last BD in the table. After this buffer is used, the CP receives incoming data using the BD pointed
to by TBASE (top of the table). The number of BDs in this table is determined only by the W bit
and overall space constraints of the dual-port RAM.
3 I Interrupt.
0 No interrupt is generated after this buffer is processed.
1 SPIE[TXB] or SPIE[TXE] are set when this buffer is processed and causes interrupts if not
masked.
4 L Last.
0 This buffer does not contain the last character of the message.
1 This buffer contains the last character of the message.
5 — Reserved, should be cleared.
6 CM Continuous mode. Valid only when the SPI is in master mode. In slave mode, it should be cleared.
0 Normal operation.
1 The CP does not clear TxBD[R] after this BD is closed, allowing the buffer to be resent
automatically when the CP next accesses this BD.
7–13 — Reserved, should be cleared.
14 UN Underrun. Indicates that the SPI encountered a transmitter underrun condition while sending the
buffer. This error occurs only when the SPI is in slave mode. The SPI updates UN after it sends the
buffer.
15 ME Multimaster error. Indicates that this buffer is closed because SPISEL was asserted when the SPI
was in master mode. A synchronization problem occurred between devices on the SPI bus. The SPI
updates ME after sending the buffer.
Table 38-9. SPI TxBD Status and Control Field Descriptions (continued)
Bits Name Description