Freescale Semiconductor MPC8260 - Manual (Page 676)

SDMA Channels and IDMA Emulation
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
19-32 Freescale Semiconductor
19.12.2 Memory-to-Peripheral Fly-By Mode—IDMA3
In the example in Table 19-16 , IDMA3 transfers data from a memory device to a 4-byte wide peripheral,
both on the 60x bus. The transfers are made by issuing 4-byte read transactions to the memory and
asserting DACK so the peripheral samples the data from the bus directly. No address is dedicated for the
peripheral, and no internal buffer is defined in this mode. The IDMA3 channel asserts DONE on the last
read transfer of the last BD to notify the peripheral that there is no data left to transfer.
Table 19-16. Example: Memory-to-Peripheral Fly-By Mode
(on 60x)–IDMA3
Important Init Values Description
DCM[FB] = 1 Fly-by mode.
DCM[LP] = x Don’t care. Transfer from memory to peripheral on the 60x bus is high priority.
DCM[DMA_WRAP] = DC Don’t care. No internal buffer is used.
DCM[ERM] = 1 Transfers from peripheral are initiated by DREQ.
DCM[DT] = 1 Assertion of DONE by the peripheral terminates the transfer, interrupt EDN is set to the
core, Current BD is closed and the next BD if valid is opened. Additional DREQ assertions
cause the new BD to be transferred.
DCM[S/D] = 01 Memory-to-peripheral mode. DONE, DREQ, and DACK are connected to the peripheral.
DCM[SINC] = 1. The memory address is incremented after every transfer.
DCM[DINC] = 1 The memory address is incremented after every transfer.
DPR_BUF The IDMA transfer buffer is not used.
IBASE = IBDPTR =
0x0030 The current BD pointer is set to the BD table base address (aligned 16 -bits[3–0]=0000).
STS = 0x0004 Transfers from memory to peripheral are always 4 bytes long (60x singles).
DTS = 0x0004 Transfers from memory to peripheral are always 4 bytes long (60x singles).
Every BD[SDTB] = 0 Memory and peripheral are on the 60x bus.
Every BD[DDTB] = 0 Memory and peripheral are on the 60x bus.
Last BD[SDN] = 1 DONE is asserted on the last transfer.
Last BD[DDN] = 1 DONE is asserted on the last transfer.
IDMR3 = 0x0400_0000 The IDMA3 mask register is programmed to enable the IDSR[OB] interrupt only.
SIMR_L = 0x0000_0100 The interrupt controller is programmed to enable interrupts from IDMA3.
PDIRA = 0x2000_0000
PPARA = 0xE000_0000
PSORA = 0xE000_0000
PODRA = 0x4000_0000 Parallel I/O registers are programmed to enable:PA[0] = DREQ3; PA[2] = DACK3; PA[1] =
DONE3.
The peripheral signals are to be connected to these lines accordingly.
RCCR = 0x0000_0080 IDMA3 configuration: DREQ is level high. DONE is high to low. request priority is higher
than the SCCs.
89FE = 0x0300 IDMA3_BASE points to 0x0300 where the parameter table base address is located for
IDMA3.