Freescale Semiconductor MPC8260 - Manual (Page 833)

Serial Management Controllers (SMCs)
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 27-21
• Transmits and receives transparently on its own set of signals using a sync signal to synchronize
the beginning of transmission and reception to an external event
• Programmable character length (4–16)
• Reverse data mode
• Continuous transmission and reception modes
• Four commands
27.4.2 SMC Transparent Channel Transmission Process
The transparent transmitter is designed to work with almost no core intervention. When the core enables
the SMC transmitter in transparent mode, it starts sending idles. The SMC immediately polls the first BD
in the transmit channel BD table and once every character time, depending on the character length (every
4 to 16 serial clocks). When there is a message to transmit, the SMC fetches the data from memory and
starts sending the message when synchronization is achieved.
Synchronization can be achieved in two ways. First, when the transmitter is connected to a TDM channel,
it can be synchronized to a time slot. Once the frame sync is received, the transmitter waits for the first bit
of its time slot before it starts transmitting. Data is sent only during the time slots defined by the TSA.
Secondly, when working with its own set of signals, the transmitter starts sending when SMSYNx is
asserted.
When a BD data is completely written to the transmit FIFO, the L bit is checked and if it is set, the SMC
writes the message status bits into the BD and clears the R bit. It then starts transmitting idles. When the
end of the current BD is reached and the L bit is not set, only R is cleared. In both cases, an interrupt is
issued according to the I bit in the BD. By appropriately setting the I bit in each BD, interrupts can be
generated after each buffer, a specific buffer, or each block is sent. The SMC then proceeds to the next BD.
If no additional buffers have been presented to the SMC for transmission and the L bit was cleared, an
underrun is detected and the SMC begins sending idles.
If the CM bit is set in the TxBD, the R bit is not cleared, so the CP can overwrite the buffer on its next
access. For instance, if a single TxBD is initialized with the CM and W bits set, the buffer is sent
continuously until R is cleared in the BD.
27.4.3 SMC Transparent Channel Reception Process
When the core enables the SMC receiver in transparent mode, it waits for synchronization before receiving
data. Once synchronization is achieved, the receiver transfers the incoming data into memory according
to the first RxBD in the table. Synchronization can be achieved in two ways. First, when the receiver is
connected to a TDM channel, it can be synchronized to a time slot. Once the frame sync is received, the
receiver waits for the first bit of its time slot to occur before reception begins. Data is received only during
the time slots defined by the TSA. Secondly, when working with its own set of signals, the receiver starts
reception when SMSYNx is asserted.
When the buffer full, the SMC clears the E bit in the BD and generates an interrupt if the I bit in the BD
is set. If incoming data exceeds the data buffer length, the SMC fetches the next BD; if it is empty, the