Freescale Semiconductor MPC8260 - Manual (Page 391)

PCI Bridge
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 9-85
9.13 DMA Controller
The PCI bridge’s DMA controller transfers blocks of data independent of the local core or PCI hosts. Data
movement occurs on the PCI and/or 60x bus. The PCI Bridge’s DMA module has four high-speed DMA
channels with an aggregate bandwidth conservatively estimated at 210 Mbytes per second, for 60x to PCI
transfer. The channels share 144 bytes of DMA-dedicated buffer space to facilitate the gathering and
sending of data. Both the local core and PCI masters can initiate a DMA transfer.
Features of the DMA controller include the following:
• 4 channels
• Concurrent execution across multiple channels with programmable bandwidth control
• All channels are accessible by local core and remote PCI masters.
• Unaligned transfer capability
• Data chaining and direct mode
• Interrupt on completed segment, chain, and error
• Supports all transfer combinations between 60x memory and PCI memory: 60x-to-60x,
PCI-to-PCI, 60x-to-PCI, and PCI-to-60x.
Figure 9-81 shows a block diagram of the DMA controller.
Figure 9-81. DMA Controller Block Diagram
9.13.1 DMA Operation
The DMA controller operates in two modes—chaining and direct. In direct mode, the software is
responsible for initializing the source, destination and byte count registers. In chaining mode, the software
first must build a chain of descriptor segments in external memory, residing either on the 60x or PCI bus,
and then initialize the current descriptor address register to point to the first descriptor segment in the
chain. In both modes, setting the start bit in the DMA mode register begins the DMA transfer.
The DMA controller supports unaligned transfers for both the source and destination addresses. It gathers
data beginning at the source address and aligns the data accordingly before sending it to the destination
DMA2 DMA3 DMA1 DMA0
Interface logic
I/O sequencer
60x bus
PCI bus