Freescale Semiconductor MPC8260 - Manual (Page 1175)

Inverse Multiplexing for ATM (IMA)
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 33-73
for the first link encountered in which a change (SCCI) is detected, it may or may not be the link under
test. An alternate method is to monitor only the link under test:
1. Don’t Monitor link for changes in SCCI for all links except link under test: ILRCNTL[MON_ICP]
= 0 (alter the corresponding Link Table Entries).
2. Monitor link under test for changes in SCCI: ILRCNTL[MON_ICP] = 1.
This will allow only changed ICP cells for the link under test to be passed on to the ICP Cell buffer.
33.5.4.12 IDCR Operation
The ATM stream reconstruction (RX) can be driven alternatively by another clock source (as opposed to
triggered by the arrival of cells/CLAV). The reconstruction rate (IMA Data Cell Rate (IDCR)) clock can
be generated by an external clock or by one of the PowerQUICC II’s baud rate generators (BRGs). Note
that the designated Rx TRL is used to record the TRLR (TRL Rate) and this is only captured once, when
a group’s GDS process is initialized. After, GDS is completed, the TRLR cannot be updated (unless the
group is re-initialized.
33.5.4.12.1 IDCR Start-up
There are some basic initialization steps that must be performed before any of the groups are activated and
make use of IDCR stream reconstruction. These steps should only be performed once:
1. Configure the base offset of the IDCR Table in the IMA Root table: IMAROOT[IDCR_BASE] = x.
2. Reset (to zero) the IDCR tick counter: IMAROOT[IDCRTICK] = 0.
3. Reset (to zero) the IDCR in Service field: IMAROOT[IDCR_SVC] = 0.
4. Reset (to zero) the IDCR_EN field: IMAROOT[IDCREN] = 0. Subsequently, any groups
operating in IDCR mode will require that this field be updated (ORed) to enable IDCR mode (e.g.
set bit for the corresponding group).
5. Since we have no active groups, configure IMAROOT[IDCR_LAST] to zero. As additional
groups are created/added, this field must also be modified accordingly with the group number
(groups are numbered 0-7).
6. Copy existing ATM parameter RAM contents to shadow RAM parameter space. For example, if
DREQ1 is used then page 8 (parameter RAM offset 0x8700) must be used as the shadow RAM. If
DREQ2 is used, then page 9 must be used, and so on. Note that the corresponding functionality
previously available and mapped to that page (e.g., MCC1, MCC2, etc.) will no longer be
available.
7. The shadow RAM must use a different address for the RCELL_TMP_BASE. Program a different
address (different than existing value being used) in RCELL_TMP_BASE. See Section 33.4.8.2.2,
“Programming the FCC Parameter Shadow.”
8. Program PIO registers: Indicate which pin is being used as the IDCR input (i.e., DREQx). The
port and pin selection is configurable and is driven by what other resources are being used on the
PowerQUICC II (e.g., Port C can be used of DREQ1 or DREQ2).