Freescale Semiconductor MPC8260 - Manual (Page 658)

SDMA Channels and IDMA Emulation
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
19-14 Freescale Semiconductor
DREQx may be configured as either edge- or level-sensitive by programming the RCCR[DRxM]. When
DREQx is configured as edge-sensitive, RCCR[EDMx] controls whether the request is generated on the
rising or falling edge; see
Section 14.3.7, “RISC Controller Configuration Register (RCCR).”
DREQx is sampled at each rising edge of the clock to determine when a valid request is asserted by the
device.
19.7.1.1 Level-Sensitive Mode
For external devices requiring very high data transfer rates, level-sensitive mode allows the IDMA to use
a maximum bandwidth to service the device. The device requests service by asserting DREQx and leaving
it asserted as long as it needs service. This mode is selected by setting the corresponding RCCR[DRxM].
The IDMA asserts DACK each time it issues a bus transaction to either read or write the peripheral. The
peripheral must use TA and TEA for data validation. DACK is the acknowledgment of the original burst
request given on DREQx. DREQx should be negated during the DACK active period to ensure that no
further transactions are performed.
When an IDMA is in external request mode and its DREQ is set to level-sensitive mode, the IDMA
requests service by the CPM whenever its DREQ signal is active. This is true regardless of whether or not
an IDMA is in progress. Therefore, whenever the IDMA's DREQ is active, all CPM peripherals with a
priority lower than the IDMA do not receive service. The IDMA priority can be configured via
RCCR[DRxQP] and, because DREQ may be active for long periods, systems that configure DREQ to be
level-sensitive must select priority option 3 for DRxQP to avoid starving other CPM peripherals (see Table
14-2 and Table 14-3). If more than one IDMA is given the same priority, the lower numbered IDMA has
priority over a higher numbered IDMA. For example, if both IDMA3 and IDMA4 are given priority
option 3, then IDMA3 will have priority over IDMA4.
In addition to the issue described in the previous paragraph, there is another issue to consider when an
IDMA is in external request mode and its DREQ is set to level-sensitive mode. When these are true and
the external peripheral device is controlled by one of the memory controllers of PowerQUICC II, such as
UPM or GPCM controller, DREQ must be negated before ‘tmax’ to prevent DREQ negation from
triggering an extra IDMA transfer cycle. Refer to the
Figure 19-7 . Note that T = 2 x CPM_CLK. In the
example shown, CPM_CLK = 133MHz, with an approximate clock cycle of 7.5ns. Therefore, T = 15ns
and DREQ must be negated no later than 15ns after the first rising edge of the bus clock after CS negation
for the peripheral.