Freescale Semiconductor MPC8260 - Manual (Page 956)

ATM Controller and AAL0, AAL1, and AAL5
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
30-36 Freescale Semiconductor
The MCC and ATM controller should be synchronized with the framer’s multi-frame block boundary. At
the ATM side, the structured block size should equal the multi-frame block size plus the size of the CAS
block so that the structured pointer, inserted by the ATM controller, points to the start of the structured data
block. At the MCC side, the MCC must to be synchronized with the super frame sync signal. This
synchronization can be achieved by external logic that triggers on the super frame sync signal and starts
delivering the frame sync to the MCC. When loss of super frame synchronization occurs, this logic should
reset and trigger again on the next super frame indication.
30.9.7 Trunk Condition
According to the Bellcore standard, the interworking function (IWF) should be able to transmit special
payload on both ATM and TDM channels to signal alarm conditions (Bellcore TR-NWT-000170). The
core can be used to generate the trunk condition payload in special buffers (or existing buffers) for the
ATM controller or MCC.
30.9.8 ATM-to-ATM Data Forwarding
Automatic data forwarding can be used to switch ATM AAL0 cells from one ATM port to another without
core intervention. The ATM receiver and transmitter should be programed to process the same BD table.
When the ATM receiver fills an AAL0 buffer, the ATM transmitter sends it. The ATM receiver and
transmitter are synchronized using the same mechanism as described for ATM-to-TDM automatic
forwarding; see
Section 30.9.1, “Automatic Data Forwarding.”
30.10 ATM Memory Structure
The ATM memory structure, described in the following sections, includes the parameter RAM, the
connection tables, OAM performance monitoring tables, the APC data structure, BD tables, the AAL1
CES sequence number protection table and the UNI statistics table.
30.10.1 Parameter RAM
When configured for ATM mode, the FCC parameter RAM is mapped as shown in Table 30-11 . Note that
there are additional parameters for AAL1 CES (refer to Table 31-4 ) and AAL2 (refer to Table 32-13 ).
Table 30-11. ATM Parameter RAM Map
Offset
1
Name Width Description
0x00–0x3
F
— — Reserved, should be cleared.
0x40 RCELL_TMP_
BASE
Hword Rx cell temporary base address. Points to a total of 64 bytes reserved
dual-port RAM area used by the CP. Should be 64 byte aligned.
User-defined offset from dual-port RAM base. (Recommended address
space: 0x3000-0x4000 or 0xB000–0xC000)
0x42 TCELL_TMP_BASE Hword Tx cell temporary base address. Points to total of 64 bytes reserved
dual-port RAM area used by the CP. Should be 64-byte aligned.
User-defined offset from dual-port RAM base. (Recommended address
space: 0x3000–0x4000 or 0xB000–0xC000)