Freescale Semiconductor MPC8260 - Manual (Page 707)

SCC UART Mode
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 21-3
3. Address/data bit (optional)
4. Parity bit (optional)
5. Stop bits
The receiver uses a clock 8
Ч, 16Ч, or 32× faster than the baud rate and samples each bit of the incoming
data three times around its center. The value of the bit is determined by the majority of those samples; if
all do not agree, the noise indication counter (NOSEC) in parameter RAM is incremented. When a
complete character has been clocked in, the contents of the receive shift register are transferred to the
receive FIFO before proceeding to the receive buffer. The CPM flags UART events, including reception
errors, in SCCE and the RxBD status and control fields.
The SCC can receive fractional stop bits. The next character’s start bit can begin any time after the three
middle samples are taken. The UART transmit shift register sends outgoing data on TXDx. Data is then
clocked synchronously with the transmit clock, which may have either an internal or external source.
Characters are sent lsb first. Only the data portion of the UART frame is stored in the buffers because start
and stop bits are generated and stripped by the SCC. A parity bit can be generated in transmission and
checked during reception; although it is not stored in the buffer, its value can be inferred from the buffer’s
reporting mechanism. Similarly, the optional address bit is not stored in the transmit or receive buffer, but
is supplied in the BD itself. Parity generation and checking includes the optional address bit.
GSMR_H[RFW] must be set for an 8-bit receive FIFO in the UART receiver.
21.3 Synchronous Mode
In synchronous mode, the controller uses a 1
× data clock for timing. The receive shift register receives
incoming data on RXDx synchronous with the clock. The bit length and format of the serial character are
defined by the control bits in the PSMR in the same way as in asynchronous mode. When a complete byte
has been clocked in, the contents of the receive shift register are transferred to the receive FIFO before
proceeding to the receive buffer. The CPM flags UART events, including reception errors, in SCCE and
the RxBD status and control fields. GSMR_H[RFW] must be set for an 8-bit receive FIFO.
The synchronous UART transmit shift register sends outgoing data on TXDx. Data is then clocked
synchronously with the transmit clock, which can have an internal or external source.
21.4 SCC UART Parameter RAM
For UART mode, the protocol-specific area of the SCC parameter RAM is mapped as in Table 21-1 .