Freescale Semiconductor MPC8260 - Manual (Page 371)

PCI Bridge
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 9-65
• Accesses to PCI configuration registers are indirect (through PCI CFG_ADDR and PCI
CFG_DATA).
A pointer located at address 0x4 of the EEPROM (right after the hard reset configuration word) defines
the beginning of the initialization table. The table should be placed beyond the reset configuration data to
avoid the EEPROM bytes dedicated to the eight possible hard reset configuration words (refer to
Section 5.4.1, “Hard Reset Configuration Word,” and Figure 9-59 ).
Figure 9-59. PCI Configuration Data Structure for the EEPROM
After a hard reset, if the auto-load enable bit has been set in the hard reset configuration word, a special
internal CP routine checks the EEPROM contents and loads the configuration data into the specified
addresses. Note that the initialization data can be loaded into any memory location (not restricted to the
PCI configuration space) by this routine.
9.12 Message Unit (I
2
O)
The embedded processor is often part of a larger system containing many processors and distributed
memory. These processors tend to work on tasks independent of the host processor(s) and other peripheral
processors in the system. Because of the independent nature of the tasks, it is necessary to provide a
communication mechanism between the peripheral processors and the rest of the system. One such method
is the use of messages. The PCI bridge provides a messaging unit to further facilitate communications
between host and peripheral. The PCI bridge’s message unit can operate with either generic messages and
door bell registers, or as an I
2
O interface.
9.12.1 Message Registers
The PCI bridge contains two inbound message registers and two outbound message registers. The registers
are each 32 bits. The inbound registers allow a remote host or PCI master to write a 32-bit value which in
0x10
0x08
Configuration byte
0x04
+0x1A
Init Table Pointer + 0x00
Init Table Pointer
+0x28
Configuration byte
Configuration byte
Address, data, size
Address, data, size
Address, data, size
Address, data, size,
LAST
+0x0C
EEPROM start address + 0x00