Freescale Semiconductor MPC8260 - Manual (Page 874)

Multi-Channel Controllers (MCCs)
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
28-26 Freescale Semiconductor
To disable AERM and enter SUERM, do the following:
1. Set SUERM_DIS bit in SS7_OPT.
2. Set parameters (T, D & SUERM) for Japanese SUERM.
3. Clear SUERM_DIS bit in SS7_OPT.
28.3.4.3.3 Disabling SUERM
When SS7_OPT[SUERM_DIS] is set, the N_cnt and D_cnt parameters are not decremented by the
microcode and no SUERM interrupt is generated. This allows these parameters to be updated, for example,
at the end of the proving period in alignment error monitoring.
Note: If the SS7 controller is in the octet counting mode (OCM) when SUERM_DIS is set, then if no idles
(only flags/data) are received while SUERM_DIS is set, then after the host updates N_cnt and D_cnt and
clears SUERM_DIS the receiver will start in OCM. However if SUERM_DIS is set while in OCM and
idles are then received then the OCM state is left.
28.3.4.4 SU Filtering—SS7 Mode
To reduce the overhead to the user software, a filtering algorithm has been adopted to allow superfluous
frames to be discarded. This algorithm compares the first 3–5 bytes (depending on the type) of the current
FISU or LSSU to the last SU received and discards the current SU if it has already been received twice.
28.3.4.4.1 Comparison Mask
A user programmable 5-byte mask exists in the parameter RAM map. When an SU is received, the
controller checks the contents of the LI field. If LI is between 0 and 2, the SU (except for the CRC portion)
will be masked according to the user programmable mask and will then be compared to the last SU
received. The state machine for the matching algorithm is in Subsection 28.3.4.4.2, “Comparison State
Machine”.
The Mask1 and Mask2 channel-specific parameters construct the 5-byte user mask. The exact format and
byte ordering are shown on
Figure 28-11 and Figure 28-12 .
28.3.4.4.2 Comparison State Machine
The following state machine exists for filtering.
msb lsb
Byte 1 Byte 2 Byte 3 Byte 4
Figure 28-11. Mask1 Format
msb lsb
Reserved, should be cleared. Byte 5
Figure 28-12. Mask2 Format