Freescale Semiconductor MPC8260 - Manual (Page 268)

60x Signals
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
7-12 Freescale Semiconductor
Negated—Indicates that an external device is not granted mastership of the data
bus.
Timing Comments Assertion—Occurs on the first clock in which the data bus is not busy and the
processor has the highest priority outstanding data transaction.
Negation—Occurs one clock after assertion.
7.2.6.2 Data Bus Busy (DBB)
The data bus busy (DBB) signal is both an input and output signal on the PowerQUICC II.
7.2.6.2.1 Data Bus Busy (DBB)—Output
Following are the state meaning and timing comments for the DBB output signal.
State Meaning Asserted—Indicates that the PowerQUICC II is the data bus master. The
PowerQUICC II always assumes data bus mastership if it needs the data bus and
determines a qualified data bus grant (see DBG).
Negated—Indicates that the PowerQUICC II is not using the data bus.
Timing Comments Assertion—Occurs during the bus clock cycle following a qualified DBG.
Negation—Occurs for a minimum of one-half bus clock cycle following the
assertion of the final TA following TEA or certain ARTRY cases.
High Impedance—Occurs after DBB is negated.
7.2.6.2.2 Data Bus Busy (DBB)—Input
Following are the state meaning and timing comments for the DBB input signal.
State Meaning Asserted—Indicates that another device is bus master.
Negated—Indicates that the data bus is free (with proper qualification, see DBG)
for use by the PowerQUICC II.
Timing Comments Assertion—Must occur when the PowerQUICC II must be prevented from using
the data bus.
Negation—May occur whenever the data bus is available.
7.2.7 Data Transfer Signals
Data transfer signals are used in the same way in both internal only and external master modes. Like the
address transfer signals, the data transfer signals are used to transmit data and to generate and monitor
parity for the data transfer. For a detailed description of how data transfer signals interact, see
Section 7.2.7, “Data Transfer Signals.”
7.2.7.1 Data Bus (D[0–63])
The data bus (D[0–63]) states have the same meanings in both internal only mode external master mode.
The data bus consists of 64 signals that are both inputs and outputs on the PowerQUICC II. Following are
the state meaning and timing comments for the data bus.