Freescale Semiconductor MPC8260 - Manual (Page 1216)

Fast Ethernet Controller
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
35-20 Freescale Semiconductor
35.18.2 Ethernet Event Register (FCCE)/Mask Register (FCCM)
The FCCE, shown in Figure 35-6 , is used as the Ethernet event register when the FCC functions as an
Ethernet controller. It generates interrupts and reports events recognized by the Ethernet channel. On
recognition of an event, the Ethernet controller sets the corresponding FCCE bit. Interrupts generated by
this register can be masked in the Ethernet mask register (FCCM).
The FCCM has the same bit format as FCCE. Setting an FCCM bit enables and clearing a bit masks the
corresponding interrupt in the FCCE.
The FCCE can be read at any time. Bits are cleared by writing ones; writing zeros does not affect bit values.
Unmasked FCCE bits must be cleared before the CP clears the internal interrupt request.
7–8 — Reserved, should be cleared.
9 PRO Promiscuous
0 Check the destination address of incoming frames.
1 Receive the frame regardless of its address. A CAM can be used for address filtering when
FSMR[CAM] is set.
10 FCE Flow control enable
0 Flow control is not enabled.
1 Flow control is enabled.
11 RSH Receive short frames
0 Discard short frames (frames smaller than the value specified in MINFLR).
1 Receive short frames.
12–20 — Reserved, should be cleared.
21 CAM CAM address matching
0 Normal operation.
1 Use the CAM for address matching; CAM result (16 bits) is added at the end of the frame.
22 BRO Broadcast address
0 Receive all frames containing the broadcast address.
1 Reject all frames containing the broadcast address unless FSMR[PRO] = 1.
23 ECM • Enable CAM miss. Valid only when the CAM is enabled. This bit interacts with RxBD[CMR].
0 Discard frames that miss in the CAM.
1 Receive frames that miss in the CAM.
24–25 CRC CRC selection
0x Reserved.
10 32-bit CCITT-CRC (Ethernet). X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 + X8 + X7 +
X5 + X4 + X2 + X1 +1. Select this to comply with Ethernet specifications.
11 Reserved.
26–31 — Reserved, should be cleared.
Figure 35-6.
Ethernet Event Register (FCCE)/Mask Register (FCCM)
0 7 8 9 10 11 12 13 14 15
Field — GRA RXC TXC TXE RXF BSY TXB RXB
Table 35-8. FPSMR Ethernet Field Descriptions (continued)
Bits Name Description