Freescale Semiconductor MPC8260 - Manual (Page 878)

Multi-Channel Controllers (MCCs)
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
28-30 Freescale Semiconductor
28.5.2 Superchannels and Receiving
The restrictions stated in Section 28.5 regarding using back-to-back timeslots with the same channel do
not apply to the receive side of the MCC. A user does not have to mark receive timeslots as
superchannelled in SIRAM programming unless transparent slot synchronization is being used (see
Section 28.5.3, “Transparent Slot Synchronization” ). Note that no SCT is used for the receive side and the
channel numbers used when programming receive SIRAM timeslots should always be that of the actual
intended MCC receive channel FIFO.
A normal MCC receive FIFO is 2 bytes and a superchannelled MCC receive FIFO is 1 byte.
28.5.3 Transparent Slot Synchronization
Transparent slot synchronization (TSS) is used to ensure that data transmission and reception for a
transparent superchannel begins on the intended timeslot of that superchannel. It is not required that the
first timeslot that appears in the SIRAM programming for a transparent superchannel be the first to send
or receive when the superchannel first starts. The user indicates which timeslot in a superchannel should
be the first to send or receive by programming the CNT and BYT fields of the superchannelled timeslots
as described in
Section 15.4.3, “Programming SIx RAM Entries.”
28.5.4 Superchannelling Programming Examples
The example in Figure 28-14 shows the SI RAM programming and the super-channel table for two
different transmitter superchannels running on the same TDM interface. One superchannel includes TDM
timeslots 1, 6, and 7, which also happen to be programmed to use MCC FIFO numbers 1, 6, and 7. The
second superchannel in this example is comprised of timeslots 2, 3, and 4 using MCC FIFOs 2, 3, and 4.
This approach of using a FIFO number which is the same as the timeslot number is arbitrary and no a
requirement.
Note that entries in the superchannel table for MCC FIFOs 1, 6 and 7 all are programmed to point to the
channel-specific and channel-extra parameters for channel 1. Superchannel table entries for MCC FIFOs
2, 3 and 4 are programmed such that these FIFOs are managed by the parameters of channel 2.