Freescale Semiconductor MPC8260 - Manual (Page 589)

Serial Interface with Time-Slot Assigner
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 15-13
Table 15-2. SI x RAM Entry (MCC = 1)
Bits Name Description
0 MCC If MCC =1, the other SI x RAM entries in this table are valid:
1 LOOP/
ECHO
Channel loopback or echo.
0 Normal mode of operation.
1 Operation depends on the following configurations:
In the receive SI x RAM, this bit selects loopback mode for this MCC channel. The channel’s
transmit data is sent to both the receiver’s input and to the data output line.
In the transmit SI
x RAM, this bit selects echo mode for this MCC channel. The channel’s receive
data is sent both to the transmitter’s line and to the receiver’s input.
To use the loop/echo modes, program the receive and transmit SI x RAMs identically, except that the
LOOP/ECHO bit should be set in only one of the entry pairs; that is, select only one of the modes
(echo or loopback, not both) per MCC slot. Also, the receive and transmit clocks must be identical.
2 SUPER MCC super channel enable. See Section 28.5, “Superchannels .”
0 The current entry refers to a regular channel.
1 The current entry refers to a super channel.
3–10 MCSEL MCC channel select. Indicates the MCC channel the bit/byte group is routed to.
• 0000_0000 selects channel 0
• 1000_000 selects channel 128 (MPC8250 and MPC8255 have only MCC2)
• 1111_1111, selects channel 255
For SI1 use values 0–127 and for SI2 use values 128–255.
Note: SI2 always reads the leftmost bit as set, even if the user has not set this bit. This ensures SI2
operates with MCC2 channel numbers.
Note: Note that the channel programming must be coherent with the MCCF; see Section 28.6,
“MCC Configuration Registers (MCCFx) .”
11–13 CNT Count.
If SUPER = 0 (normal mode), CNT indicates the number of bits/bytes (according to the BYT bit) that
the routing select of this entry controls. 000 = 1 bit/byte; 111 = 8 bits/bytes.
If SUPER = 1 (MCC super channel), CNT and BYT together indicate whether the current entry is
the first byte of the MCC super channel.
CNT= 000 and BYT = 1—The current entry is the first byte of this MCC super channel.
CNT= 111 and BYT = 0—The current entry is not the first byte of this MCC super channel.
Note: Because all SI
x RAM entries relating to super channels must be 1-byte in resolution, only the
above two combinations of CNT and BYT are allowed when SUPER = 1.
14 BYT Byte resolution
0 Bit resolution. The CNT value indicates the number of bits in this group.
1 Byte resolution. The CNT value indicates the number of bytes in this group.
15 LST Last entry in the RAM. Whenever the SI x RAM is used, LST must be set in one of the Tx or Rx
entries of each group. Even if all entries of a group are used, LST must still be set in the last entry.
0 Not the last entry in this section of the route RAM.
1 Last entry in this RAM. After this entry, the SI waits for the sync signal to start the next frame.
Note: There must be only an even number of entries in an SI
x RAM frame, because LST is active
only in odd-numbered entries (assuming the entry count starts with 0). Therefore, to obtain
an even number of entries, an entry may need to be split into two entries.
Also note that, to avoid errors in switching to and from shadow SI RAM, the last entry in SI RAM
should not be programmed to 1-bit resolution (i.e. CNT = 000 and BYT = 0).